ZHCSA13P November 2008 – February 2021 TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28023 , TMS320F28023-Q1 , TMS320F28026 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027 , TMS320F28027-Q1 , TMS320F28027F , TMS320F28027F-Q1
PRODUCTION DATA
The 2802x/280200 devices incorporate a method to reduce the device current consumption. Because each peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current consumption even further. Table 8-1 indicates the typical reduction in current consumption achieved by turning off the clocks.
PERIPHERAL MODULE(1)(3) | IDD CURRENT REDUCTION (mA) |
---|---|
ADC | 2(2) |
I2C | 3 |
ePWM | 2 |
eCAP | 2 |
SCI | 2 |
SPI | 2 |
COMP/DAC | 1 |
HRPWM | 3 |
CPU-TIMER | 1 |
Internal zero-pin oscillator | 0.5 |
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
The baseline IDD current (current when the core is executing a dummy loop with no peripherals enabled) is 45 mA, typical. To arrive at the IDD current for a given application, the current-drawn by the peripherals (enabled by that application) must be added to the baseline IDD current.
Following are other methods to reduce power consumption further: