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ZHCSA13P November 2008 – February 2021 TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28023 , TMS320F28023-Q1 , TMS320F28026 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027 , TMS320F28027-Q1 , TMS320F28027F , TMS320F28027F-Q1

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

PT|48
- MTQF003C
DA|38
- MPDS502

散热焊盘机械数据 (封装 | 引脚)

DA|38
- QFND327

订购信息

9.9.1.1.3.1 ADC Electrical Characteristics

PARAMETER		MIN	TYP	MAX	UNIT
DC SPECIFICATIONS
Resolution		12			Bits
ADC clock	60-MHz device	0.001		60	MHz
Sample Window	28027/26/23/22	7		64	ADC Clocks
Sample Window	28021/20/200	14		64	ADC Clocks
ACCURACY
INL (Integral nonlinearity) at ADC Clock ≤ 30 MHz⁽¹⁾		–4		4	LSB
DNL (Differential nonlinearity) at ADC Clock ≤ 30 MHz, no missing codes		–1		1	LSB
Offset error ⁽²⁾	Executing Device_Cal function	–20	0	20	LSB
Offset error ⁽²⁾	Executing periodic self-recalibration⁽³⁾	–4	0	4	LSB
Overall gain error with internal reference		–60		60	LSB
Overall gain error with external reference		–40		40	LSB
Channel-to-channel offset variation		–4		4	LSB
Channel-to-channel gain variation		–4		4	LSB
ADC temperature coefficient with internal reference			–50		ppm/°C
ADC temperature coefficient with external reference			–20		ppm/°C
V_REFLO			–100		µA
V_REFHI			100		µA
ANALOG INPUT
Analog input voltage with internal reference		0		3.3	V
Analog input voltage with external reference		V_REFLO		V_REFHI	V
V_REFLO input voltage⁽⁴⁾		V_SSA		V_SSA	V
V_REFHI input voltage⁽⁵⁾	with V_REFLO = V_SSA	1.98		V_DDA	V
Input capacitance			5		pF
Input leakage current			±5		μA

(1) INL will degrade when the ADC input voltage goes above V_DDA.

(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and V_REFHI - V_REFLO for external reference.

(3) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be performed as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset Calibration" section of the Analog-to-Digital Converter and Comparator chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual.

(4) V_REFLO is always connected to V_SSA .

(5) V_REFHI must not exceed V_DDA when using either internal or external reference modes. Because V_REFHI is tied to ADCINA0 , the input signal on ADCINA0 must not exceed V_DDA.