Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the burden of monitoring the V_DD and V_DDIO supply rails from the application board. The purpose of the POR is to create a clean reset throughout the device during the entire power-up procedure. The trip point is a looser, lower trip point than the BOR, which watches for dips in the V_DD or V_DDIO rail during device operation. The POR function is present on both V_DD and V_DDIO rails at all times. After initial device power-up, the BOR function is present on V_DDIO at all times, and on V_DD when the internal VREG is enabled ( VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below their respective trip point. V_DD BOR and overvoltage trip points are outside of the recommended operating voltages. Proper device operation cannot be ensured. If overvoltage or undervoltage conditions affecting the system is a concern for an application, an external voltage supervisor should be added. Figure 9-6 shows the VREG, POR, and BOR. To disable both the V_DD and V_DDIO BOR functions, a bit is provided in the BORCFG register. For details, see the System Control chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual.

A. WDRST is the reset signal from the CPU watchdog.

B. PBRS is the reset signal from the POR/BOR module.

Figure 9-6 VREG + POR + BOR + Reset Signal Connectivity