The device contains one I2C Serial Port. Figure 9-34 shows how the I2C peripheral module interfaces within the device.

The I2C module has the following features:

• Compliance with the Philips Semiconductors I²C-bus specification (version 2.1):
  • Support for 1-bit to 8-bit format transfers
  • 7-bit and 10-bit addressing modes
  • General call
  • START byte mode
  • Support for multiple master-transmitters and slave-receivers
  • Support for multiple slave-transmitters and master-receivers
  • Combined master transmit/receive and receive/transmit mode
  • Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
• One 4-word receive FIFO and one 4-word transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions:
  • Transmit-data ready
  • Receive-data ready
  • Register-access ready
  • No-acknowledgment received
  • Arbitration lost
  • Stop condition detected
  • Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode

For more information on the I2C, see the Inter-Integrated Circuit Module (I2C) chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual.

A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the SYSCLKOUT rate.

B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low-power operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.

Figure 9-34 I2C Peripheral Module Interfaces

The registers in Table 9-26 configure and control the I2C port operation.