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ZHCSA13P November 2008 – February 2021 TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28023 , TMS320F28023-Q1 , TMS320F28026 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027 , TMS320F28027-Q1 , TMS320F28027F , TMS320F28027F-Q1

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机械数据 (封装 | 引脚)

PT|48
- MTQF003C

散热焊盘机械数据 (封装 | 引脚)

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9.9.3.2.1 SPI Slave Mode External Timing (Clock Phase = 0)

NO.⁽¹⁾⁽²⁾⁽⁴⁾⁽³⁾⁽⁵⁾	PARAMETER		MIN	MAX	UNIT
12	t_c(SPC)S	Cycle time, SPICLK	4t_c(SYSCLK)		ns
13	t_w(SPC1)S	Pulse duration, SPICLK first pulse	2t_c(SYSCLK) – 1		ns
14	t_w(SPC2)S	Pulse duration, SPICLK second pulse	2t_c(SYSCLK) – 1		ns
15	t_d(SOMI)S	Delay time, SPICLK to SPISOMI valid		21	ns
16	t_v(SOMI)S	Valid time, SPISOMI data valid after SPICLK	0		ns
19	t_su(SIMO)S	Setup time, SPISIMO valid before SPICLK	1.5t_c(SYSCLK)		ns
20	t_h(SIMO)S	Hold time, SPISIMO data valid after SPICLK	1.5t_c(SYSCLK)		ns
25	t_su(STE)S	Setup time, SPISTE active before SPICLK	1.5t_c(SYSCLK)		ns
26	t_h(STE)S	Hold time, SPISTE inactive after SPICLK	1.5t_c(SYSCLK)		ns

(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2) t_c(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3) t_c(LCO) = LSPCLK cycle time

(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

Figure 9-31 SPI Slave Mode External Timing (Clock Phase = 0)