ZHCSIE4A June 2018 – July 2018 TMS320F28035-EP
PRODUCTION DATA.
In Figure 5-1, the following apply:
ADDRESS RANGE | PROGRAM AND DATA SPACE |
---|---|
0x3E 8000 to 0x3E 9FFF | Sector H (8K × 16) |
0x3E A000 to 0x3E BFFF | Sector G (8K × 16) |
0x3E C000 to 0x3E DFFF | Sector F (8K × 16) |
0x3E E000 to 0x3E FFFF | Sector E (8K × 16) |
0x3F 0000 to 0x3F 1FFF | Sector D (8K × 16) |
0x3F 2000 to 0x3F 3FFF | Sector C (8K × 16) |
0x3F 4000 to 0x3F 5FFF | Sector B (8K × 16) |
0x3F 6000 to 0x3F 7F7F | Sector A (8K × 16) |
0x3F 7F80 to 0x3F 7FF5 | Program to 0x0000 when using the
Code Security Module |
0x3F 7FF6 to 0x3F 7FF7 | Boot-to-Flash Entry Point
(program branch instruction here) |
0x3F 7FF8 to 0x3F 7FFF | Security Password (128-Bit)
(Do not program to all zeros) |
NOTE
Table 5-4 shows how to handle these memory locations.
ADDRESS | FLASH | |
---|---|---|
CODE SECURITY ENABLED | CODE SECURITY DISABLED | |
0x3F 7F80 to 0x3F 7FEF | Fill with 0x0000 | Application code and data |
0x3F 7FF0 to 0x3F 7FF5 | Reserved for data only |
Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as written. Because of the pipeline, a write immediately followed by a read to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The CPU supports a block protection mode where a region of memory can be protected so that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it protects the selected zones.
The wait states for the various spaces in the memory map area are listed in Table 5-5.
AREA | WAIT STATES (CPU) | COMMENTS |
---|---|---|
M0 and M1 SARAMs | 0-wait | Fixed |
Peripheral Frame 0 | 0-wait | |
Peripheral Frame 1 | 0-wait (writes) | Cycles can be extended by peripheral generated ready. |
2-wait (reads) | Back-to-back write operations to Peripheral Frame 1 registers will incur a 1-cycle stall (1-cycle delay). | |
Peripheral Frame 2 | 0-wait (writes) | Fixed. Cycles cannot be extended by the peripheral. |
2-wait (reads) | ||
Peripheral Frame 3 | 0-wait (writes) | Assumes no conflict between CPU and CLA. |
2-wait (reads) | Cycles can be extended by peripheral-generated ready. | |
L0 SARAM | 0-wait data and program | Assumes no CPU conflicts |
L1 SARAM | 0-wait data and program | Assumes no CPU conflicts |
L2 SARAM | 0-wait data and program | Assumes no CPU conflicts |
L3 SARAM | 0-wait data and program | Assumes no CPU conflicts |
OTP | Programmable | Programmed through the Flash registers. |
1-wait minimum | 1-wait is minimum number of wait states allowed. | |
FLASH | Programmable | Programmed through the Flash registers. |
0-wait Paged min | ||
1-wait Random min
Random ≥ Paged |
||
FLASH Password | 16-wait fixed | Wait states of password locations are fixed. |
Boot-ROM | 0-wait |