ZHCS009J November   2010  – September 2021 TMS320F28062 , TMS320F28062F , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28067 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069F , TMS320F28069M

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1. 3.1 功能方框图
    2. 3.2 系统器件图
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 TMS320F2806x Current Consumption at 90-MHz SYSCLKOUT
      2. 7.5.2 Reducing Current Consumption
      3. 7.5.3 Current Consumption Graphs (VREG Enabled)
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics
      1. 7.7.1 PFP PowerPAD Package
      2. 7.7.2 PZP PowerPAD Package
      3. 7.7.3 PN Package
      4. 7.7.4 PZ Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  Debug Probe Connection Without Signal Buffering for the MCU
    10. 7.10 Parameter Information
      1. 7.10.1 Timing Parameter Symbology
      2. 7.10.2 General Notes on Timing Parameters
    11. 7.11 Test Load Circuit
    12. 7.12 Power Sequencing
      1. 7.12.1 Reset ( XRS) Timing Requirements
      2. 7.12.2 Reset ( XRS) Switching Characteristics
    13. 7.13 Clock Specifications
      1. 7.13.1 Device Clock Table
        1. 7.13.1.1 2806x Clock Table and Nomenclature (90-MHz Devices)
        2. 7.13.1.2 Device Clocking Requirements/Characteristics
        3. 7.13.1.3 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 7.13.2 Clock Requirements and Characteristics
        1. 7.13.2.1 XCLKIN Timing Requirements – PLL Enabled
        2. 7.13.2.2 XCLKIN Timing Requirements – PLL Disabled
        3. 7.13.2.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 7.14 Flash Timing
      1. 7.14.1 Flash/OTP Endurance for T Temperature Material
      2. 7.14.2 Flash/OTP Endurance for S Temperature Material
      3. 7.14.3 Flash/OTP Endurance for Q Temperature Material
      4. 7.14.4 Flash Parameters at 90-MHz SYSCLKOUT
      5. 7.14.5 Flash/OTP Access Timing
      6. 7.14.6 Flash Data Retention Duration
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1  CPU
      2. 8.1.2  Control Law Accelerator (CLA)
      3. 8.1.3  Viterbi, Complex Math, CRC Unit (VCU)
      4. 8.1.4  Memory Bus (Harvard Bus Architecture)
      5. 8.1.5  Peripheral Bus
      6. 8.1.6  Real-Time JTAG and Analysis
      7. 8.1.7  Flash
      8. 8.1.8  M0, M1 SARAMs
      9. 8.1.9  L4 SARAM, and L0, L1, L2, L3, L5, L6, L7, and L8 DPSARAMs
      10. 8.1.10 Boot ROM
        1. 8.1.10.1 Debug Boot
        2. 8.1.10.2 GetMode
        3. 8.1.10.3 Peripheral Pins Used by the Bootloader
      11. 8.1.11 Security
      12. 8.1.12 Peripheral Interrupt Expansion (PIE) Block
      13. 8.1.13 External Interrupts (XINT1 to XINT3)
      14. 8.1.14 Internal Zero Pin Oscillators, Oscillator, and PLL
      15. 8.1.15 Watchdog
      16. 8.1.16 Peripheral Clocking
      17. 8.1.17 Low-power Modes
      18. 8.1.18 Peripheral Frames 0, 1, 2, 3 (PFn)
      19. 8.1.19 General-Purpose Input/Output (GPIO) Multiplexer
      20. 8.1.20 32-Bit CPU-Timers (0, 1, 2)
      21. 8.1.21 Control Peripherals
      22. 8.1.22 Serial Port Peripherals
    2. 8.2 Memory Maps
    3. 8.3 Register Maps
    4. 8.4 Device Debug Registers
    5. 8.5 VREG, BOR, POR
      1. 8.5.1 On-chip VREG
        1. 8.5.1.1 Using the On-chip VREG
        2. 8.5.1.2 Disabling the On-chip VREG
      2. 8.5.2 On-chip Power-On Reset (POR) and Brownout Reset (BOR) Circuit
    6. 8.6 System Control
      1. 8.6.1 Internal Zero Pin Oscillators
      2. 8.6.2 Crystal Oscillator Option
      3. 8.6.3 PLL-Based Clock Module
      4. 8.6.4 USB and HRCAP PLL Module (PLL2)
      5. 8.6.5 Loss of Input Clock (NMI Watchdog Function)
      6. 8.6.6 CPU Watchdog Module
    7. 8.7 Low-power Modes Block
    8. 8.8 Interrupts
      1. 8.8.1 External Interrupts
        1. 8.8.1.1 External Interrupt Electrical Data/Timing
          1. 8.8.1.1.1 External Interrupt Timing Requirements
          2. 8.8.1.1.2 External Interrupt Switching Characteristics
    9. 8.9 Peripherals
      1. 8.9.1  CLA Overview
      2. 8.9.2  Analog Block
        1. 8.9.2.1 Analog-to-Digital Converter (ADC)
          1. 8.9.2.1.1 Features
          2. 8.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. 8.9.2.1.2.1 External ADC Start-of-Conversion Switching Characteristics
          3. 8.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. 8.9.2.1.3.1 ADC Electrical Characteristics
            2. 8.9.2.1.3.2 ADC Power Modes
            3. 8.9.2.1.3.3 Internal Temperature Sensor
              1. 8.9.2.1.3.3.1 Temperature Sensor Coefficient
            4. 8.9.2.1.3.4 ADC Power-Up Control Bit Timing
              1. 8.9.2.1.3.4.1 ADC Power-Up Delays
            5. 8.9.2.1.3.5 ADC Sequential and Simultaneous Timings
        2. 8.9.2.2 ADC MUX
        3. 8.9.2.3 Comparator Block
          1. 8.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. 8.9.2.3.1.1 Electrical Characteristics of the Comparator/DAC
      3. 8.9.3  Detailed Descriptions
      4. 8.9.4  Serial Peripheral Interface (SPI) Module
        1. 8.9.4.1 SPI Master Mode Electrical Data/Timing
          1. 8.9.4.1.1 SPI Master Mode External Timing (Clock Phase = 0)
          2. 8.9.4.1.2 SPI Master Mode External Timing (Clock Phase = 1)
        2. 8.9.4.2 SPI Slave Mode Electrical Data/Timing
          1. 8.9.4.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
          2. 8.9.4.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 8.9.5  Serial Communications Interface (SCI) Module
      6. 8.9.6  Multichannel Buffered Serial Port (McBSP) Module
        1. 8.9.6.1 McBSP Electrical Data/Timing
          1. 8.9.6.1.1 McBSP Transmit and Receive Timing
            1. 8.9.6.1.1.1 McBSP Timing Requirements
            2. 8.9.6.1.1.2 McBSP Switching Characteristics
          2. 8.9.6.1.2 McBSP as SPI Master or Slave Timing
            1. 8.9.6.1.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. 8.9.6.1.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. 8.9.6.1.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. 8.9.6.1.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. 8.9.6.1.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. 8.9.6.1.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. 8.9.6.1.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. 8.9.6.1.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      7. 8.9.7  Enhanced Controller Area Network (eCAN) Module
      8. 8.9.8  Inter-Integrated Circuit (I2C)
        1. 8.9.8.1 I2C Electrical Data/Timing
          1. 8.9.8.1.1 I2C Timing Requirements
          2. 8.9.8.1.2 I2C Switching Characteristics
      9. 8.9.9  Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1 to ePWM8)
        1. 8.9.9.1 ePWM Electrical Data/Timing
          1. 8.9.9.1.1 ePWM Timing Requirements
          2. 8.9.9.1.2 ePWM Switching Characteristics
        2. 8.9.9.2 Trip-Zone Input Timing
          1. 8.9.9.2.1 Trip-Zone Input Timing Requirements
      10. 8.9.10 High-Resolution PWM (HRPWM)
        1. 8.9.10.1 HRPWM Electrical Data/Timing
          1. 8.9.10.1.1 High-Resolution PWM Characteristics
      11. 8.9.11 Enhanced Capture Module (eCAP1)
        1. 8.9.11.1 eCAP Electrical Data/Timing
          1. 8.9.11.1.1 Enhanced Capture (eCAP) Timing Requirement
          2. 8.9.11.1.2 eCAP Switching Characteristics
      12. 8.9.12 High-Resolution Capture Modules (HRCAP1 to HRCAP4)
        1. 8.9.12.1 HRCAP Electrical Data/Timing
          1. 8.9.12.1.1 High-Resolution Capture (HRCAP) Timing Requirements
      13. 8.9.13 Enhanced Quadrature Encoder Modules (eQEP1, eQEP2)
        1. 8.9.13.1 eQEP Electrical Data/Timing
          1. 8.9.13.1.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
          2. 8.9.13.1.2 eQEP Switching Characteristics
      14. 8.9.14 JTAG Port
      15. 8.9.15 General-Purpose Input/Output (GPIO) MUX
        1. 8.9.15.1 GPIO Electrical Data/Timing
          1. 8.9.15.1.1 GPIO Output Timing
            1. 8.9.15.1.1.1 General-Purpose Output Switching Characteristics
          2. 8.9.15.1.2 GPIO Input Timing
            1. 8.9.15.1.2.1 General-Purpose Input Timing Requirements
          3. 8.9.15.1.3 Sampling Window Width for Input Signals
          4. 8.9.15.1.4 Low-Power Mode Wakeup Timing
            1. 8.9.15.1.4.1 IDLE Mode Timing Requirements
            2. 8.9.15.1.4.2 IDLE Mode Switching Characteristics
            3. 8.9.15.1.4.3 STANDBY Mode Timing Requirements
            4. 8.9.15.1.4.4 STANDBY Mode Switching Characteristics
            5. 8.9.15.1.4.5 HALT Mode Timing Requirements
            6. 8.9.15.1.4.6 HALT Mode Switching Characteristics
      16. 8.9.16 Universal Serial Bus (USB)
        1. 8.9.16.1 USB Electrical Data/Timing
          1. 8.9.16.1.1 USB Input Ports DP and DM Timing Requirements
          2. 8.9.16.1.2 USB Output Ports DP and DM Switching Characteristics
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Device and Development Support Tool Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 术语表
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

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6.2.1 Signal Descriptions

PIN NAMEPIN NO.I/O/Z(1)DESCRIPTION
PZ
PZP		PN
PFP
JTAG
TRST1210IJTAG test reset with internal pulldown (PD). TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored.
NOTE:TRST is an active-high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application. (↓)
TCKSee GPIO38ISee GPIO38. JTAG test clock with internal pullup. (↑)
TMSSee GPIO36ISee GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (↑)
TDISee GPIO35ISee GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (↑)
TDOSee GPIO37O/ZSee GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK.
(8-mA drive)
FLASH
VDD3VFL46373.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.
TEST24536I/OTest Pin. Reserved for TI. Must be left unconnected.
CLOCK
XCLKOUTSee GPIO18O/ZSee GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.
XCLKINSee GPIO19 and GPIO38ISee GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be disabled through bit 14 in the CLKCTL register. If a crystal or resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register.
NOTE: Designs that use the GPIO38/XCLKIN/TCK pin to supply an external clock for normal device operation may need to incorporate some hooks to disable this path during debug using the JTAG connector. This is to prevent contention with the TCK signal, which is active during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to clock the device.
X16048IOn-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to GND.
X25947OOn-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, it must be left unconnected.
RESET
XRS119I/ODDevice Reset (in) and Watchdog Reset (out). These devices have a built-in power-on reset (POR) and brownout reset (BOR) circuitry. During a power-on or brownout condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3F FFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain device with an internal pullup. (↑) If this pin is driven by an external device, it should be done using an open-drain device.
ADC, COMPARATOR, ANALOG I/O
ADCINA716–IADC Group A, Channel 7 input
ADCINA61714IADC Group A, Channel 6 input
COMP3AIComparator Input 3A
AIO6I/ODigital AIO 6
ADCINA51815IADC Group A, Channel 5 input
ADCINA41916IADC Group A, Channel 4 input
COMP2AIComparator Input 2A
AIO4I/ODigital AIO 4
ADCINA320–IADC Group A, Channel 3 input
ADCINA22117IADC Group A, Channel 2 input
COMP1AIComparator Input 1A
AIO2I/ODigital AIO 2
ADCINA12218IADC Group A, Channel 1 input
ADCINA02319IADC Group A, Channel 0 input.
NOTE: VREFHI and ADCINA0 share the same pin on the 80-pin PN and PFP devices and their use is mutually exclusive to one another.
VREFHI2419ADC External Reference High – only used when in ADC external reference mode. See Section 8.9.2.1.
NOTE: VREFHI and ADCINA0 share the same pin on the 80-pin PN and PFP devices and their use is mutually exclusive to one another.
ADCINB735–IADC Group B, Channel 7 input
ADCINB63427IADC Group B, Channel 6 input
COMP3BIComparator Input 3B
AIO14I/ODigital AIO 14
ADCINB53326IADC Group B, Channel 5 input
ADCINB43225IADC Group B, Channel 4 input
COMP2BIComparator Input 2B
AIO12I/ODigital AIO12
ADCINB331–IADC Group B, Channel 3 input
ADCINB23024IADC Group B, Channel 2 input
COMP1BIComparator Input 1B
AIO10I/ODigital AIO 10
ADCINB12923IADC Group B, Channel 1 input
ADCINB02822IADC Group B, Channel 0 input
VREFLO2721ADC External Reference Low.
NOTE: VREFLO is always connected to VSSA on the 80-pin PN and PFP devices.
CPU AND I/O POWER
VDDA2520Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin.
VSSA2621Analog Ground Pin.
NOTE: VREFLO is always connected to VSSA on the 80-pin PN and PFP devices.
VDD32CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground. Higher value capacitors may be used.
1412
3729
6351
8165
9172
VDDIO54Digital I/O Buffers Power Pin. Single supply source when VREG is enabled. Place a decoupling capacitor on each pin. The exact value should be determined by the system voltage regulation solution.
1311
3830
6149
7963
9374
VSS43Digital Ground Pins
1513
3628
4738
6250
8064
9273
VOLTAGE REGULATOR CONTROL SIGNAL
VREGENZ9071IInternal voltage regulator (VREG) enable with internal pulldown. Tie directly to VSS (low) to enable the internal 1.8-V VREG. Tie directly to VDDIO (high) to disable the VREG and use an external 1.8-V supply.
GPIO AND PERIPHERAL SIGNALS(2)
GPIO08769I/O/ZGeneral-purpose input/output 0
EPWM1AOEnhanced PWM1 Output A and HRPWM channel
Reserved–Reserved
Reserved–Reserved
GPIO18668I/O/ZGeneral-purpose input/output 1
EPWM1BOEnhanced PWM1 Output B
Reserved–Reserved
COMP1OUTODirect output of Comparator 1
GPIO28467I/O/ZGeneral-purpose input/output 2
EPWM2AOEnhanced PWM2 Output A and HRPWM channel
Reserved–Reserved
Reserved–Reserved
GPIO38366I/O/ZGeneral-purpose input/output 3
EPWM2BOEnhanced PWM2 Output B
SPISOMIAI/OSPI-A slave out, master in
COMP2OUTODirect output of Comparator 2
GPIO497I/O/ZGeneral-purpose input/output 4
EPWM3AOEnhanced PWM3 output A and HRPWM channel
Reserved–Reserved
Reserved–Reserved
GPIO5108I/O/ZGeneral-purpose input/output 5
EPWM3BOEnhanced PWM3 output B
SPISIMOAI/OSPI-A slave in, master out
ECAP1I/OEnhanced Capture input/output 1
GPIO65846I/O/ZGeneral-purpose input/output 6
EPWM4AOEnhanced PWM4 output A and HRPWM channel
EPWMSYNCIIExternal ePWM sync pulse input
EPWMSYNCOOExternal ePWM sync pulse output
GPIO75745I/O/ZGeneral-purpose input/output 7
EPWM4BOEnhanced PWM4 output B
SCIRXDAISCI-A receive data
ECAP2I/OEnhanced Capture input/output 2
GPIO85443I/O/ZGeneral-purpose input/output 8
EPWM5AOEnhanced PWM5 output A and HRPWM channel
Reserved–Reserved
ADCSOCAOOADC start-of-conversion A
GPIO94939I/O/ZGeneral-purpose input/output 9
EPWM5BOEnhanced PWM5 output B
SCITXDBOSCI-B transmit data
ECAP3I/OEnhanced Capture input/output 3
GPIO107460I/O/ZGeneral-purpose input/output 10
EPWM6AOEnhanced PWM6 output A and HRPWM channel
Reserved–Reserved
ADCSOCBOOADC start-of-conversion B
GPIO117359I/O/ZGeneral-purpose input/output 11
EPWM6BOEnhanced PWM6 output B
SCIRXDBISCI-B receive data
ECAP1I/OEnhanced Capture input/output 1
GPIO124435I/O/ZGeneral-purpose input/output 12
TZ1ITrip Zone input 1
SCITXDAOSCI-A transmit data
SPISIMOBI/OSPI-B slave in, master out
GPIO139575I/O/ZGeneral-purpose input/output 13
TZ2ITrip Zone input 2
Reserved–Reserved
SPISOMIBI/OSPI-B slave out, master in
GPIO149676I/O/ZGeneral-purpose input/output 14
TZ3ITrip zone input 3
SCITXDBOSCI-B transmit data
SPICLKBI/OSPI-B clock input/output
GPIO158870I/O/ZGeneral-purpose input/output 15
ECAP2I/OEnhanced Capture input/output 2
SCIRXDBISCI-B receive data
SPISTEBI/OSPI-B slave transmit enable input/output
GPIO165544I/O/ZGeneral-purpose input/output 16
SPISIMOAI/OSPI-A slave in, master out
Reserved–Reserved
TZ2ITrip Zone input 2
GPIO175242I/O/ZGeneral-purpose input/output 17
SPISOMIAI/OSPI-A slave out, master in
Reserved–Reserved
TZ3ITrip zone input 3
GPIO185141I/O/ZGeneral-purpose input/output 18
SPICLKAI/OSPI-A clock input/output
SCITXDBOSCI-B transmit data
XCLKOUTO/ZOutput clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.
GPIO196452I/O/ZGeneral-purpose input/output 19
XCLKINIExternal Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken not to enable this path for clocking if it is being used for the other peripheral functions.
SPISTEAI/OSPI-A slave transmit enable input/output
SCIRXDBISCI-B receive data
ECAP1I/OEnhanced Capture input/output 1
GPIO2065I/O/ZGeneral-purpose input/output 20
EQEP1AIEnhanced QEP1 input A
MDXAOMcBSP transmit serial data
COMP1OUTODirect output of Comparator 1
GPIO2176I/O/ZGeneral-purpose input/output 21
EQEP1BIEnhanced QEP1 input B
MDRAIMcBSP receive serial data
COMP2OUTODirect output of Comparator 2
GPIO229878I/O/ZGeneral-purpose input/output 22
EQEP1SI/OEnhanced QEP1 strobe
MCLKXAI/OMcBSP transmit clock
SCITXDBOSCI-B transmit data
GPIO2321I/O/ZGeneral-purpose input/output 23
EQEP1II/OEnhanced QEP1 index
MFSXAI/OMcBSP transmit frame synch
SCIRXDBISCI-B receive data
GPIO249777I/O/ZGeneral-purpose input/output 24
ECAP1I/OEnhanced Capture input/output 1
EQEP2AIEnhanced QEP2 input A.
NOTE: eQEP2 is available only in the PZ and PZP packages.
SPISIMOBI/OSPI-B slave in, master out
GPIO253931I/O/ZGeneral-purpose input/output 25
ECAP2I/OEnhanced Capture input/output 2
EQEP2BIEnhanced QEP2 input B.
NOTE: eQEP2 is available only in the PZ and PZP packages.
SPISOMIBI/OSPI-B slave out, master in
GPIO267862I/O/ZGeneral-purpose input/output 26
ECAP3I/OEnhanced Capture input/output 3
EQEP2II/OEnhanced QEP2 index.
NOTE: eQEP2 is available only in the PZ and PZP packages.
SPICLKBI/OSPI-B clock input/output
USB0DP(3)I/OPositive Differential half of USB signal. To enable USB functionality on this pin, set the USBIOEN bit in the GPACTRL2 register.
GPIO277761I/O/ZGeneral-purpose input/output 27
HRCAP2IHigh-Resolution Input Capture 2
EQEP2SI/OEnhanced QEP2 strobe.
NOTE: eQEP2 is available only in the PZ and PZP packages.
SPISTEBI/OSPI-B slave transmit enable input/output
USB0DM(3)I/ONegative Differential half of USB signal. To enable USB functionality on this pin, set the USBIOEN bit in the GPACTRL2 register.
GPIO285040I/O/ZGeneral-purpose input/output 28
SCIRXDAISCI-A receive data
SDAAI/ODI2C data open-drain bidirectional port
TZ2ITrip zone input 2
GPIO294334I/O/ZGeneral-purpose input/output 29
SCITXDAOSCI-A transmit data
SCLAI/ODI2C clock open-drain bidirectional port
TZ3ITrip zone input 3
GPIO304133I/O/ZGeneral-purpose input/output 30
CANRXAICAN receive
EQEP2II/OEnhanced QEP2 index.
NOTE: eQEP2 is available only in the PZ and PZP packages.
EPWM7AOEnhanced PWM7 Output A and HRPWM channel
GPIO314032I/O/ZGeneral-purpose input/output 31
CANTXAOCAN transmit
EQEP2SI/OEnhanced QEP2 strobe.
NOTE: eQEP2 is available only in the PZ and PZP packages.
EPWM8AOEnhanced PWM8 Output A and HRPWM channel
GPIO329979I/O/ZGeneral-purpose input/output 32
SDAAI/ODI2C data open-drain bidirectional port
EPWMSYNCIIEnhanced PWM external sync pulse input
ADCSOCAOOADC start-of-conversion A
GPIO3310080I/O/ZGeneral-purpose input/output 33
SCLAI/ODI2C clock open-drain bidirectional port
EPWMSYNCOOEnhanced PWM external synch pulse output
ADCSOCBOOADC start-of-conversion B
GPIO346855I/O/ZGeneral-purpose input/output 34
COMP2OUTODirect output of Comparator 2
Reserved–Reserved
COMP3OUTODirect output of Comparator 3
GPIO357157I/O/ZGeneral-purpose input/output 35
TDIIJTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.
Reserved–Reserved
Reserved–Reserved
Reserved–Reserved
GPIO367258I/O/ZGeneral-purpose input/output 36
TMSIJTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK.
Reserved–Reserved
Reserved–Reserved
Reserved–Reserved
GPIO377056I/O/ZGeneral-purpose input/output 37
TDOO/ZJTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive).
Reserved–Reserved
Reserved–Reserved
Reserved–Reserved
GPIO386754I/O/ZGeneral-purpose input/output 38
XCLKINIExternal Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken to not enable this path for clocking if it is being used for the other functions.
TCKIJTAG test clock with internal pullup
Reserved–Reserved
Reserved–Reserved
Reserved–Reserved
GPIO396653I/O/ZGeneral-purpose input/output 39
Reserved–Reserved
Reserved–Reserved
Reserved–Reserved
GPIO4082–I/O/ZGeneral-purpose input/output 40
EPWM7AOEnhanced PWM7 output A and HRPWM channel
SCITXDBOSCI-B transmit data
Reserved–Reserved
GPIO4176–I/O/ZGeneral-purpose input/output 41
EPWM7BOEnhanced PWM7 output B
SCIRXDBISCI-B receive data
Reserved–Reserved
GPIO421–I/O/ZGeneral-purpose input/output 42
EPWM8AOEnhanced PWM8 output A and HRPWM channel
TZ1ITrip zone input 1
COMP1OUTODirect output of Comparator 1
GPIO438–I/O/ZGeneral-purpose input/output 43
EPWM8BOEnhanced PWM8 output B
TZ2ITrip zone input 2
COMP2OUTODirect output of Comparator 2
GPIO4456–I/O/ZGeneral-purpose input/output 44
MFSRAI/OMcBSP receive frame synch
SCIRXDBISCI-B receive data
EPWM7BOEnhanced PWM7 output B
GPIO5042–I/O/ZGeneral-purpose input/output 50
EQEP1AIEnhanced QEP1 input A
MDXAOMcBSP transmit serial data
TZ1ITrip zone input 1
GPIO5148–I/O/ZGeneral-purpose input/output 51
EQEP1BIEnhanced QEP1 input B
MDRAIMcBSP receive serial data
TZ2ITrip zone input 2
GPIO5253–I/O/ZGeneral-purpose input/output 52
EQEP1SI/OEnhanced QEP1 strobe
MCLKXAI/OMcBSP transmit clock
TZ3ITrip zone input 3
GPIO5365–I/O/ZGeneral-purpose input/output 53
EQEP1II/OEnhanced QEP1 index
MFSXAI/OMcBSP transmit frame synch
Reserved–Reserved
GPIO5469–I/O/ZGeneral-purpose input/output 54
SPISIMOAI/OSPI-A slave in, master out
EQEP2AIEnhanced QEP2 input A
HRCAP1IHigh-Resolution Input Capture 1
GPIO5575–I/O/ZGeneral-purpose input/output 55
SPISOMIAI/OSPI-A slave out, master in
EQEP2BIEnhanced QEP2 input B
HRCAP2IHigh-Resolution Input Capture 2
GPIO5685–I/O/ZGeneral-purpose input/output 56
SPICLKAI/OSPI-A clock input/output
EQEP2II/OEnhanced QEP2 index
HRCAP3IHigh-Resolution Input Capture 3
GPIO5789–I/O/ZGeneral-purpose input/output 57
SPISTEAI/OSPI-A slave transmit enable input/output
EQEP2SI/OEnhanced QEP2 strobe
HRCAP4IHigh-Resolution Input Capture 4
GPIO5894–I/O/ZGeneral-purpose input/output 58
MCLKRAI/OMcBSP receive clock
SCITXDBOSCI-B transmit data
EPWM7AOEnhanced PWM7 output A and HRPWM channel
(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown
(2) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the GPIO block and the path to the JTAG block from a pin is enabled or disabled based on the condition of the TRST signal. See the Systems Control and Interrupts chapter of the TMS320x2806x Technical Reference Manual .
(3) Depending on your USB application, additional pins may be required to maintain compliance with the USB 2.0 Specification. For more information, see the Universal Serial Bus (USB) Controller chapter of the TMS320x2806x Technical Reference Manual .
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