6.2.3 Enhanced Analog-to-Digital Converter (ADC) Module

A simplified functional block diagram of the ADC module is shown in Figure 6-4. The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:

• 12-bit ADC core with built-in S/H
• Analog input: 0.0 V to 3.0 V (voltages above 3.0 V produce full-scale conversion results)
• Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS
• 16-channel, MUXed inputs
• Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can be programmed to select any 1 of 16 input channels
• Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (that is, two cascaded 8-state sequencers)
• Sixteen result registers (individually addressable) to store conversion values
  • The digital value of the input analog voltage is derived by:
  
• Multiple triggers as sources for the start-of-conversion (SOC) sequence
  • S/W – software immediate start
  • EVA – Event manager A (multiple event sources within EVA)
  • EVB – Event manager B (multiple event sources within EVB)
• Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
• Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize conversions
• EVA and EVB triggers can operate independently in dual-sequencer mode
• Sample-and-hold (S/H) acquisition time window has separate prescale control

The ADC module in the F281x has been enhanced to provide flexible interface to event managers A and B. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80 ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules to service event managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 6-4 shows the block diagram of the F281x ADC module.

The two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.

Figure 6-4 Block Diagram of the F281x ADC Module

To obtain the specified accuracy of the ADC, proper board layout is critical. To the best extent possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins (V_DDA1/V_DDA2, AVDDREFBG) from the digital supply. For better accuracy and ESD protection, unused ADC inputs should be connected to analog ground.

Notes:

1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:

ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the clock to the register will still function. This is necessary to make sure all registers and modes go into their default reset state. The analog module will, however, be in a low-power inactive state. As soon as reset goes high, then the clock to the registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the registers will be enabled and the analog module will be enabled. There will be a certain time delay (ms range) before the ADC is stable and can be used.

HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC module is powered. If high, the ADC module goes into low-power mode. The HALT mode will stop the clock to the CPU, which will stop the HSPCLK. Therefore the ADC register logic will be turned off indirectly.

Figure 6-5 shows the ADC pin-biasing for internal reference and Figure 6-6 shows the ADC pin-biasing for external reference.

A. Provide access to this pin in PCB layouts. Intended for test purposes only.

B. Use 24.9 kΩ for ADC clock range 1–18.75 MHz; use 20 kΩ for ADC clock range 18.75–25 MHz.

C. TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent ceramic capacitor

D. External decoupling capacitors are recommended on all power pins.

E. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.

Figure 6-5 ADC Pin Connections With Internal Reference

A. External decoupling capacitors are recommended on all power pins.

B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.

C. Use 24.9 kΩ for ADC clock range 1–18.75 MHz; use 20 kΩ for ADC clock range 18.75–25 MHz.

D. It is recommended that buffered external references be provided with a voltage difference of (ADCREFP – ADCREFM) = 1 V ± 0.1% or better.
External reference is enabled using bit 8 in the ADCTRL3 Register at ADC power up. In this mode, the accuracy of external reference is critical for overall gain. The voltage ADCREFP – ADCREFM will determine the overall accuracy. Do not enable internal references when external references are connected to ADCREFP and ADCREFM. See the TMS320x281x DSP Analog-to-Digital Converter (ADC) Reference Guide for more information.

Figure 6-6 ADC Pin Connections With External Reference

The ADC operation is configured, controlled, and monitored by the registers listed in Table 6-6.