The ADC module described here is a successive approximation (SAR) style ADC with selectable resolution of 12 bits or 16 bits. This section refers to the analog circuits of the converter as the “core,” and includes the channel-select MUX, the sample-and-hold (S/H) circuit, the successive approximation circuits, voltage reference circuits, and other analog support circuits. The digital circuits of the converter are referred to as the “wrapper” and include logic for programmable conversions, result registers, interfaces to analog circuits, interfaces to the peripheral buses, post-processing circuits, and interfaces to other on-chip modules.

Each ADC module consists of a single sample-and-hold (S/H) circuit. The ADC module is designed to be duplicated multiple times on the same chip, allowing simultaneous sampling or independent operation of multiple ADCs. The ADC wrapper is start-of-conversion (SOC)-based (see the SOC Principle of Operation section of the Analog-to-Digital Converter (ADC) chapter in the TMS320F28P65x Real-Time Microcontrollers Technical Reference Manual).

Each ADC has the following features:

• Selectable resolution of 12 bits or 16 bits
• Ratiometric external reference set by VREFHI/VREFLO
• Selectable internal reference of 2.5 V or 3.3 V
• Single-ended or differential signal mode
• Input multiplexer with up to 26 channels (single ended) or 10 channels (differential)
• 16 configurable SOCs
• 16 individually addressable result registers
• External analog input mux selection per SOC, up to 4 bits
• Multiple trigger sources
  • Software immediate start
  • All ePWMs: ADCSOC A or B
  • GPIO XINT2
  • CPU Timers 0/1/2
  • ADCINT1/2
  • ECAP events in capture mode (CEVT1, CEVT2, CEVT3, and CEVT4) and APWM mode (period match, compare match, or both).
  • Global software trigger for multiple ADCs
• Four flexible PIE interrupts
• Burst-mode triggering option
• Hardware oversampling mode up to 128x, with configurable trigger spread delay
• Hardware undersampling mode
• Trigger phase delay function
• Four post-processing blocks, each with:
  • Saturating offset calibration
  • Error from setpoint calculation
  • High, low, and zero-crossing compare, with interrupt and ePWM trip capability
  • Trigger-to-sample delay capture
  • Absolute value calculation
  • 24-bit accumulation register for oversampling, with configurable binary shift
  • Minimum/maximum calculation for outlier rejection

The block diagram for the ADC core and ADC wrapper are shown in Figure 6-49.

Figure 6-49 ADC Module Block Diagram