米6体育平台手机版

SPRSP69B July 2023 – November 2023 TMS320F28P650DK , TMS320F28P659DK-Q1

PRODMIX

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

PZP|100
ZEJ|256
PTP|176

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.13.2.2.6 ADC Characteristics 12-bit Differential

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
General
ADCCLK Conversion Cycles	200-MHz SYSCLK	10.1		11	ADCCLKs
Power Up Time	External Reference mode			500	µs
	Internal Reference mode			5000	µs
	Internal Reference mode, when switching between 2.5-V range and 3.3-V range.			5000	µs
VREFHI input current⁽¹⁾			130		µA
Internal Reference Capacitor Value⁽²⁾		2.2			µF
External Reference Capacitor Value⁽²⁾		2.2			µF
DC Characteristics
Gain Error	Internal reference	–45		45	LSB
Gain Error	External reference	–5	±3	5	LSB
Offset Error⁽⁶⁾		–5	±2	5	LSB
Channel-to-Channel Gain Error⁽⁴⁾			±2		LSB
Channel-to-Channel Offset Error⁽⁴⁾			±2		LSB
ADC-to-ADC Gain Error⁽⁵⁾	Identical VREFHI and VREFLO for all ADCs		±4		LSB
ADC-to-ADC Offset Error⁽⁵⁾	Identical VREFHI and VREFLO for all ADCs		±1		LSB
DNL Error		>–1	±0.5	1	LSB
INL Error		–2	±0.5	2	LSB
ADC-to-ADC Isolation	VREFHI = 2.5 V, synchronous ADCs	–1		1	LSBs
ADC-to-ADC Isolation	VREFHI = 2.5 V, asynchronous ADCs		Not supported		LSBs
AC Characteristics
SNR⁽³⁾	VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1 via PLL		72.1		dB
SNR⁽³⁾	VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from INTOSC via PLL		65.2		dB
THD⁽³⁾	VREFHI = 2.5 V, fin = 100 kHz		-86.9		dB
SFDR⁽³⁾	VREFHI = 2.5 V, fin = 100 kHz		90		dB
SINAD⁽³⁾	VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1 via PLL		72		dB
SINAD⁽³⁾	VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from INTOSC via PLL		65.1		dB
ENOB⁽³⁾	VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1, Single ADC		11.7		bits
	VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1, synchronous ADCs		11.7
	VREFHI = 2.5 V, fin = 100 kHz, SYSCLK from X1, asynchronous ADCs		Not Supported
PSRR	VDD = 1.2-V DC + 100mV DC up to Sine at 1 kHz		60		dB
	VDD = 1.2-V DC + 100 mV DC up to Sine at 300 kHz		57
	VDDA = 3.3-V DC + 200 mV DC up to Sine at 1 kHz		60
	VDDA = 3.3-V DC + 200 mV Sine at 900 kHz		57

(1) Load current on VREFHI increases when ADC input is greater than VDDA. This causes inaccurate conversions.

(2) A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable.

(3) IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and crosstalk.

(4) Variation across all channels belonging to the same ADC module.

(5) Worst case variation compared to other ADC modules.

(6) ADC result output can be automatically adjusted for offset error by using the PPB Offset Calibration feature.