CCM-R5F also monitors the inputs to the interconnect coming from the checker Cortex-R5F core. The input signals to the interconnect are compared against their default clamped values. The checker core must not generate any bus transaction to the interconnect system as all bus transactions are carried out through the main CPU core. If any signal value is different from its clamped value, an error signal is generated. The error response in case of a detected transaction is sent to ESM.

In addition to bus monitoring the checker CPU core, the CCM-R5F will also monitor several other critical signals from other masters residing in other power domains. This is to ensure an inadvertent bus transaction from an unused power domain can be detected. To enable detection of unwanted transaction from an unused master, the power domain in which the master to be monitored will need to be configured in OFF power state through the PMM module.