ZHCSA84C October   2012  – May 2018 TMS570LS0332 , TMS570LS0432

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PZ QFP Package Pinout (100-Pin)
    2. 4.2 Terminal Functions
      1. 4.2.1  High-End Timer (N2HET)
      2. 4.2.2  Enhanced Quadrature Encoder Pulse Modules (eQEP)
      3. 4.2.3  General-Purpose Input/Output (GPIO)
      4. 4.2.4  Controller Area Network Interface Modules (DCAN1, DCAN2)
      5. 4.2.5  Multibuffered Serial Peripheral Interface (MibSPI1)
      6. 4.2.6  Standard Serial Peripheral Interface (SPI2)
      7. 4.2.7  Local Interconnect Network Controller (LIN)
      8. 4.2.8  Multibuffered Analog-to-Digital Converter (MibADC)
      9. 4.2.9  System Module
      10. 4.2.10 Error Signaling Module (ESM)
      11. 4.2.11 Main Oscillator
      12. 4.2.12 Test/Debug Interface
      13. 4.2.13 Flash
      14. 4.2.14 Core Supply
      15. 4.2.15 I/O Supply
      16. 4.2.16 Core and I/O Supply Ground Reference
    3. 4.3 Output Multiplexing and Control
      1. 4.3.1 Notes on Output Multiplexing
      2. 4.3.2 General Rules for Multiplexing Control Registers
    4. 4.4 Special Multiplexed Options
      1. 4.4.1 Filtering for eQEP Inputs
        1. 4.4.1.1 eQEPA Input
        2. 4.4.1.2 eQEPB Input
        3. 4.4.1.3 eQEPI Input
        4. 4.4.1.4 eQEPS Input
      2. 4.4.2 N2HET PIN_nDISABLE Input Port
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Switching Characteristics Over Recommended Operating Conditions for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption
    8. 5.8  Thermal Resistance Characteristics for PZ
    9. 5.9  Input/Output Electrical Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
  6. 6System Information and Electrical Specifications
    1. 6.1  Voltage Monitor Characteristics
      1. 6.1.1 Important Considerations
      2. 6.1.2 Voltage Monitor Operation
      3. 6.1.3 Supply Filtering
    2. 6.2  Power Sequencing and Power-On Reset
      1. 6.2.1 Power-Up Sequence
      2. 6.2.2 Power-Down Sequence
      3. 6.2.3 Power-On Reset: nPORRST
        1. 6.2.3.1 nPORRST Electrical and Timing Requirements
    3. 6.3  Warm Reset (nRST)
      1. 6.3.1 Causes of Warm Reset
      2. 6.3.2 nRST Timing Requirements
    4. 6.4  ARM Cortex-R4 CPU Information
      1. 6.4.1 Summary of ARM Cortex-R4 CPU Features
      2. 6.4.2 ARM Cortex-R4 CPU Features Enabled by Software
      3. 6.4.3 Dual Core Implementation
      4. 6.4.4 Duplicate clock tree after GCLK
      5. 6.4.5 ARM Cortex-R4 CPU Compare Module (CCM) for Safety
      6. 6.4.6 CPU Self-Test
        1. 6.4.6.1 Application Sequence for CPU Self-Test
        2. 6.4.6.2 CPU Self-Test Clock Configuration
        3. 6.4.6.3 CPU Self-Test Coverage
    5. 6.5  Clocks
      1. 6.5.1 Clock Sources
        1. 6.5.1.1 Main Oscillator
          1. 6.5.1.1.1 Timing Requirements for Main Oscillator
        2. 6.5.1.2 Low-Power Oscillator
          1. 6.5.1.2.1 Features
          2. 6.5.1.2.2 LPO Electrical and Timing Specifications
        3. 6.5.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.5.1.3.1 Block Diagram
          2. 6.5.1.3.2 PLL Timing Specifications
      2. 6.5.2 Clock Domains
        1. 6.5.2.1 Clock Domain Descriptions
        2. 6.5.2.2 Mapping of Clock Domains to Device Modules
      3. 6.5.3 Clock Test Mode
    6. 6.6  Clock Monitoring
      1. 6.6.1 Clock Monitor Timings
      2. 6.6.2 External Clock (ECLK) Output Functionality
      3. 6.6.3 Dual Clock Comparator
        1. 6.6.3.1 Features
        2. 6.6.3.2 Mapping of DCC Clock Source Inputs
    7. 6.7  Glitch Filters
    8. 6.8  Device Memory Map
      1. 6.8.1 Memory Map Diagram
      2. 6.8.2 Memory Map Table
      3. 6.8.3 Master/Slave Access Privileges
    9. 6.9  Flash Memory
      1. 6.9.1 Flash Memory Configuration
      2. 6.9.2 Main Features of Flash Module
      3. 6.9.3 ECC Protection for Flash Accesses
      4. 6.9.4 Flash Access Speeds
    10. 6.10 Flash Program and Erase Timings for Program Flash
    11. 6.11 Flash Program and Erase Timings for Data Flash
    12. 6.12 Tightly Coupled RAM Interface Module
      1. 6.12.1 Features
      2. 6.12.2 TCRAMW ECC Support
    13. 6.13 Parity Protection for Accesses to peripheral RAMs
    14. 6.14 On-Chip SRAM Initialization and Testing
      1. 6.14.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.14.1.1 Features
        2. 6.14.1.2 PBIST RAM Groups
      2. 6.14.2 On-Chip SRAM Auto Initialization
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 Real-Time Interrupt Module
      1. 6.16.1 Features
      2. 6.16.2 Block Diagrams
      3. 6.16.3 Clock Source Options
    17. 6.17 Error Signaling Module
      1. 6.17.1 Features
      2. 6.17.2 ESM Channel Assignments
    18. 6.18 Reset / Abort / Error Sources
    19. 6.19 Digital Windowed Watchdog
    20. 6.20 Debug Subsystem
      1. 6.20.1 Block Diagram
      2. 6.20.2 Debug Components Memory Map
      3. 6.20.3 JTAG Identification Code
      4. 6.20.4 Debug ROM
      5. 6.20.5 JTAG Scan Interface Timings
      6. 6.20.6 Advanced JTAG Security Module
      7. 6.20.7 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1 Peripheral Legend
    2. 7.2 Multibuffered 12-Bit Analog-to-Digital Converter
      1. 7.2.1 Features
      2. 7.2.2 Event Trigger Options
        1. 7.2.2.1 MIBADC Event Trigger Hookup
      3. 7.2.3 ADC Electrical and Timing Specifications
      4. 7.2.4 Performance (Accuracy) Specifications
        1. 7.2.4.1 MibADC Nonlinearity Errors
        2. 7.2.4.2 MibADC Total Error
    3. 7.3 General-Purpose Input/Output
      1. 7.3.1 Features
    4. 7.4 Enhanced High-End Timer (N2HET)
      1. 7.4.1 Features
      2. 7.4.2 N2HET RAM Organization
      3. 7.4.3 Input Timing Specifications
      4. 7.4.4 N2HET Checking
        1. 7.4.4.1 Output Monitoring using Dual Clock Comparator (DCC)
      5. 7.4.5 Disabling N2HET Outputs
      6. 7.4.6 High-End Timer Transfer Unit (N2HET)
        1. 7.4.6.1 Features
        2. 7.4.6.2 Trigger Connections
    5. 7.5 Controller Area Network (DCAN)
      1. 7.5.1 Features
      2. 7.5.2 Electrical and Timing Specifications
    6. 7.6 Local Interconnect Network Interface (LIN)
      1. 7.6.1 LIN Features
    7. 7.7 Multibuffered / Standard Serial Peripheral Interface
      1. 7.7.1 Features
      2. 7.7.2 MibSPI Transmit and Receive RAM Organization
      3. 7.7.3 MibSPI Transmit Trigger Events
        1. 7.7.3.1 MIBSPI1 Event Trigger Hookup
      4. 7.7.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.7.5 SPI Slave Mode I/O Timings
    8. 7.8 Enhanced Quadrature Encoder (eQEP)
      1. 7.8.1 Clock Enable Control for eQEPx Modules
      2. 7.8.2 Using eQEPx Phase Error
      3. 7.8.3 Input Connections to eQEPx Modules
      4. 7.8.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
  8. 8器件和文档支持
    1. 8.1  器件支持
      1. 8.1.1 开发支持
        1. 8.1.1.1 开始使用
      2. 8.1.2 器件命名规则
    2. 8.2  文档支持
      1. 8.2.1 米6体育平台手机版_好二三四 (TI) 相关文档
    3. 8.3  相关链接
    4. 8.4  Community Resources
    5. 8.5  商标
    6. 8.6  静电放电警告
    7. 8.7  术语表
    8. 8.8  器件识别码寄存器
      1. Table 8-2 器件 ID 位分配寄存器字段说明
    9. 8.9  芯片识别寄存器
    10. 8.10 模块认证
      1. 8.10.1 DCAN 认证
      2. 8.10.2 LIN 认证
        1. 8.10.2.1 LIN 主控模式
        2. 8.10.2.2 LIN 受控模式 - 固定波特率
        3. 8.10.2.3 LIN 受控模式 - 自适应波特率
  9. 9机械、封装和可订购米6体育平台手机版_好二三四附录
    1. 9.1 封装信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.18 Reset / Abort / Error Sources

Table 6-27 Reset/Abort/Error Sources

ERROR SOURCE SYSTEM MODE ERROR RESPONSE ESM HOOKUP
GROUP.CHANNEL
CPU TRANSACTIONS
Precise write error (NCNB/Strongly Ordered) User/Privilege Precise Abort (CPU) n/a
Precise read error (NCB/Device or Normal) User/Privilege Precise Abort (CPU) n/a
Imprecise write error (NCB/Device or Normal) User/Privilege Imprecise Abort (CPU) n/a
Illegal instruction User/Privilege Undefined Instruction Trap (CPU)(1) n/a
MPU access violation User/Privilege Abort (CPU) n/a
SRAM
B0 TCM (even) ECC single error (correctable) User/Privilege ESM 1.26
B0 TCM (even) ECC double error (noncorrectable) User/Privilege Abort (CPU), ESM → nERROR 3.3
B0 TCM (even) uncorrectable error (that is, redundant address decode) User/Privilege ESM → NMI → nERROR 2.6
B0 TCM (even) address bus parity error User/Privilege ESM → NMI → nERROR 2.10
B1 TCM (odd) ECC single error (correctable) User/Privilege ESM 1.28
B1 TCM (odd) ECC double error (noncorrectable) User/Privilege Abort (CPU), ESM → nERROR 3.5
B1 TCM (odd) uncorrectable error (that is, redundant address decode) User/Privilege ESM → NMI → nERROR 2.8
B1 TCM (odd) address bus parity error User/Privilege ESM → NMI → nERROR 2.12
FLASH WITH CPU BASED ECC
FMC correctable error - Bus1 and Bus2 interfaces (does not include accesses to EEPROM bank) User/Privilege ESM 1.6
FMC uncorrectable error - Bus1 accesses
(does not include address parity error)		 User/Privilege Abort (CPU), ESM → nERROR 3.7
FMC uncorrectable error - Bus2 accesses
(does not include address parity error and EEPROM bank accesses)		 User/Privilege ESM → nERROR 3.7
FMC uncorrectable error - address parity error on Bus1 accesses User/Privilege ESM → NMI → nERROR 2.4
FMC correctable error - Accesses to EEPROM bank User/Privilege ESM 1.35
FMC uncorrectable error - Accesses to EEPROM bank User/Privilege ESM 1.36
HIGH-END TIMER TRANSFER UNIT (HTU)
NCNB (Strongly Ordered) transaction with slave error response User/Privilege Interrupt → VIM n/a
External imprecise error (Illegal transaction with ok response) User/Privilege Interrupt → VIM n/a
Memory access permission violation User/Privilege ESM 1.9
Memory parity error User/Privilege ESM 1.8
N2HET
Memory parity error User/Privilege ESM 1.7
MIBSPI
MibSPI1 memory parity error User/Privilege ESM 1.17
MIBADC
MibADC Memory parity error User/Privilege ESM 1.19
DCAN
DCAN1 memory parity error User/Privilege ESM 1.21
DCAN2 memory parity error User/Privilege ESM 1.23
PLL
PLL slip error User/Privilege ESM 1.10
CLOCK MONITOR
Clock monitor interrupt User/Privilege ESM 1.11
DCC
DCC error User/Privilege ESM 1.30
CCM-R4
Self test failure User/Privilege ESM 1.31
Compare failure User/Privilege ESM → NMI → nERROR 2.2
VIM
Memory parity error User/Privilege ESM 1.15
VOLTAGE MONITOR
VMON out of voltage range n/a Reset n/a
CPU SELF-TEST (LBIST)
CPU Self-test (LBIST) error User/Privilege ESM 1.27
PIN MULTIPLEXING CONTROL
Mux configuration error User/Privilege ESM 1.37
eFuse CONTROLLER
eFuse Controller Autoload error User/Privilege ESM → nERROR 3.1
eFuse Controller - Any bit set in the error status register User/Privilege ESM 1.40
eFuse Controller self-test error User/Privilege ESM 1.41
WINDOWED WATCHDOG
WWD Nonmaskable Interrupt exception n/a ESM => NMI => nERROR 2.24
ERRORS REFLECTED IN THE SYSESR REGISTER
Power-Up Reset n/a Reset n/a
Oscillator fail / PLL slip(2) n/a Reset n/a
Watchdog exception n/a Reset n/a
CPU Reset (driven by the CPU STC) n/a Reset n/a
Software Reset n/a Reset n/a
External Reset n/a Reset n/a
(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of the CPU.
(2) Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |