The TMUX6136 is implemented with simple transmission gate topology, as shown in Figure 7-14. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

Figure 7-14 Transmission Gate Topology

The TMUX6136 utilizes special charge-injection cancellation circuitry that reduces the drain (D)-to-source (Sx) charge injection to as low as –0.4 pC at V_S = 0 V, as shown in Figure 7-15.

Figure 7-15 Charge Injection vs Drain Voltage