The TMUX7234 has a transmission gate topology, as shown in Figure 7-1. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

Figure 7-1 Transmission Gate Topology

The TMUX7234 contains specialized architecture to reduce charge injection on the source (Sx). To further reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the drain (D). This will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the drain (D) instead of the source (Sx). As a general rule of thumb, Cp should be 20x larger than the equivalent load capacitance on the source (Sx). Figure 7-2 shows charge injection variation with different compensation capacitors on the drain side. This plot was captured on the TMUX7219 as part of the TMUX72xx family with a 100pF load capacitance.

Figure 7-2 Charge Injection Compensation