Figure 7-1 shows how the TMUX7236 device has a transmission gate topology. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

Figure 7-1 Transmission Gate Topology

The TMUX7236 contains specialized architecture to reduce charge injection on the Drain (Dx). To further reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the Source (Sx). This will push excess charge from the switch transition into the compensation capacitor on the Source (Sx) instead of the Drain (Dx). As a general rule, Cp should be 20x larger than the equivalent load capacitance on the Drain (Dx). Figure 7-2 shows charge injection variation with different compensation capacitors on the Source side. Figure 7-2 was captured on the TMUX7219 as part of the TMUX72xx family with a 100 pF load capacitance.

Figure 7-2 Charge Injection Compensation