ZHCS354D June   2011  – July 2016 TPD12S015A

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ICC
    6. 6.6  Electrical Characteristics: High-Speed ESD Lines: Dx, CLK
    7. 6.7  Electrical Characteristics: DC-DC Converter
    8. 6.8  Electrical Characteristics: Passive Components
    9. 6.9  Electrical Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A/x_B Ports)
    10. 6.10 Electrical Characteristics: Voltage Level Shifter: CEC Lines (x_A/x_B Ports)
    11. 6.11 Electrical Characteristics: Voltage Level Shifter: HPD Line (x_A/x_B Ports)
    12. 6.12 Electrical Characteristics: LS_OE, CT_CP_HPD
    13. 6.13 Electrical Characteristics: I/O Capacitance
    14. 6.14 Switching Characteristics
    15. 6.15 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.2 V
    16. 6.16 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.2 V
    17. 6.17 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.2 V
    18. 6.18 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.5 V
    19. 6.19 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.5 V
    20. 6.20 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.5 V
    21. 6.21 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.8 V
    22. 6.22 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.8 V
    23. 6.23 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 1.8 V
    24. 6.24 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 2.5 V
    25. 6.25 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 2.5 V
    26. 6.26 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 2.5 V
    27. 6.27 Switching Characteristics: Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 3.3 V
    28. 6.28 Switching Characteristics: Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 3.3 V
    29. 6.29 Switching Characteristics: Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 3.3 V
    30. 6.30 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rise-Time Accelerators
      2. 8.3.2 Internal Pullup Resistor
      3. 8.3.3 Undervoltage Lockout
      4. 8.3.4 Soft Start
      5. 8.3.5 DDC/CEC Level Shifting Function
      6. 8.3.6 DDC/CEC Level Shifting Function When VCCA = 1.8 V
      7. 8.3.7 CEC Level Shifting Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable
      2. 8.4.2 Power Save Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
        4. 9.2.2.4 CEC, HPD, SCL, SDA Level Shifting Function
        5. 9.2.2.5 ESD
        6. 9.2.2.6 Ground Offset Consideration
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Pin Configuration and Functions

YFF Package
28-Pin DSBGA
Top View
TPD12S015A po_llse19.gif
For package dimensions, see 机械、封装和可订购信息

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
5VOUT F1 Power Out DC-DC output. The 5-V power pin can supply 55 mA of regulated current to the HDMI receiver. Separate DC-DC converter control pin CT_CP_HPD disables the DC-DC converter when operating at low-power mode.
CEC_A B2 I/O System-side CEC bus I/O. This pin is bidirectional and referenced to VCCA.
CEC_B D3 I/O HDMI-side CEC bus I/O. This pin is bidirectional and referenced to the 3.3-V internal supply.
CLK–, CLK+ G4, F4 ESD High-speed ESD clamp: provides ESD protection to the high-speed HDMI differential data lines
CT_CP_HPD D1 Control DC-DC Enable. Enables the DC-DC converter and HPD circuitry when CT_CP_HPD = H. The CT_CP_HPD is referenced to VCCA.
D0–, D0+,
D1– , D1+,
D2–, D2+
E4, D4,
C4, B4,
A4, A3
ESD High-speed ESD clamp: provides ESD protection to the high-speed HDMI differential data lines
FB E1 I Feedback input. This pin is a feedback control pin for the DC-DC converter. It must be connected to 5VOUT.
GND B3, C3,
D2, E2
Ground Device ground
HPD_A C2 O System-side output for the hot plug detect. This pin is unidirectional and is referenced to VCCA.
HPD_B G3 I HDMI-side input for the hot plug detect. This pin is unidirectional and is referenced to 5VOUT.
LS_OE A1 Control Level shifter enable. This pin is referenced to VCCA. Enables SCL, SDA, CEC level shifters, and LDO when LS_OE = H.
PGND G1 Analog Ground DC-DC converter ground. This pin must be tied externally to the system GND plane. See Layout Guidelines.
SCL_A B1 I/O System-side input and output for I2C bus. This pin is bidirectional and referenced to VCCA.
SCL_B E3 I/O HDMI-side input and output for I2C bus. This pin is bidirectional and referenced to 5VOUT.
SDA_A C1 I/O System-side input and output for I2C bus. This pin is bidirectional and referenced to VCCA.
SDA_B F3 I/O HDMI-side input and output for I2C bus. This pin is bidirectional and referenced to 5VOUT.
SW F2 I Switch input. This pin is the inductor input for the DC-DC converter.
VBAT G2 Supply Battery supply. This voltage is typically 2.3 V to 5.5 V
VCCA A2 Supply System-side supply. this voltage is typically 1.2 V to 3.3 V from the core microcontroller.

Table 1. YFF Package Pin Mapping

1 2 3 4
A LS_OE VCCA D2+ D2–
B SCL_A CEC_A GND D1+
C SDA_A HPD_A GND D1–
D CT_CP_HPD GND CEC_B D0+
E FB GND SCL_B D0–
F 5VOUT SW SDA_B CLK+
G PGND VBAT HPD_B CLK–