8.3.1 Rise-Time Accelerators

The HDMI cable side of the DDC lines incorporates rise-time accelerators to support the high capacitive load on the HDMI cable side. The rise time accelerator boosts the cable side DDC signal independent of which side of the bus is releasing the signal.

8.3.2 Internal Pullup Resistor

The TPD12S015A has incorporated all the required pullup and pulldown resistors at the interface pins. The system is designed to work properly with no external pullup resistors on the DDC, CEC, and HPD lines. For proper system operation, no external resistors must be placed at the A and B ports. If there is internal pullups at the host processor, they must be disabled.

8.3.3 Undervoltage Lockout

The undervoltage lockout circuit prevents the DC-DC converter from malfunctioning at low input voltages and from excessive discharge of the battery. It disables the output stage of the converter once the falling V_IN trips the undervoltage lockout threshold V_BATUV. The undervoltage lockout threshold V_BATUV for falling V_IN is typically 2 V. The device starts operation once the rising V_IN trips undervoltage lockout threshold V_BATUV again at typical 2.1 V.

8.3.4 Soft Start

The DC-DC converter has an internal soft-start circuit that controls the ramp-up of the output voltage. The output voltage reaches its nominal value within t_Start of typically 250 µs after CT_CP_HPD pin has been pulled to high level. The output voltage ramps up from 5% to its nominal value within t_Ramp of 300 µs. This limits the inrush current in the converter during start-up, and prevents possible input voltage drops when a battery or high impedance power source is used. During soft start, the switch current limit is reduced to 300 mA until the output voltage reaches V_IN. Once the output voltage trips this threshold, the device operates with its nominal current limit ILIMF.

8.3.5 DDC/CEC Level Shifting Function

The TPD12S015A enables DDC translation from V_CCA (system side) voltage levels to 5-V (HDMI cable side) voltage levels without degradation of system performance. The TPD12S015A contains two bidirectional open-drain buffers specifically designed to support up-translation and down-translation between the low voltage, V_CCA side DDC-bus and the 5-V DDC-bus. The port B I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered. After power up and with the LS_OE and CT_CP_HPD pins high, a low level on port A (below approximately V_ILC = 0.08 × V_CCA V) turns the corresponding port B driver (either SDA or SCL) on and drives port B down to V_OLB V. When port A rises above approximately 0.10 × V_CCA V, the port B pulldown driver is turned off, and the internal pullup resistor pulls the pin high. When port B falls first and goes below 0.3 × 5VOUT, a CMOS hysteresis input buffer detects the falling edge, turns on the port A driver, and pulls port A down to approximately V_OLA = 0.16 × V_CCA V. The port B pulldown is not enabled unless the port A voltage goes below V_ILC. If the port A low voltage goes below V_ILC, the port B pulldown driver is enabled until port A rises above (V_ILC + ΔV_T-HYSTA); then port B, if not externally driven LOW, continues to rise being pulled up by the internal pullup resistor.

Figure 15. DDC/CEC Level Shifter Block Diagram

8.3.6 DDC/CEC Level Shifting Function When V_CCA = 1.8 V

• The threshold of CMP1 is approximately 150 mV ± the 40 mV of total hysteresis.
• The comparator trips for a falling waveform at approximately 130 mV
• The comparator trips for a rising waveform at approximately 170 mV
• To be recognized as a zero, the level at Port A must first go below 130 mV (VILC in spec) and then stay below 170 mV (VILA in spec)
• To be recognized as a one, the level at A must first go above 170 mV and then stay above 130 mV
• VILC is set to 110 mV to give some margin to the 130 mV
• VILA is set to 140 mV to give some margin to the 170 mV
• VIHA is set to 70% of V_CCA to be consistent with standard CMOS levels

Figure 16. DDC/CEC Level Shifter Operation (B to A Direction)

8.3.7 CEC Level Shifting Function

The CEC level shift function operates in the same manner as the DDC lines except that the CEC line does not need the rise time accelerator function.

8.4.1 Enable

The DC-DC converter is enabled when the CT_CP_HPD is set to high. At first, the internal reference is activated and the internal analog circuits are settled. Afterwards, the soft start is activated and the output voltage is ramped up. The output voltage reaches its nominal value in typically 250 μs after the device has been enabled. The CT_CP_HPD input can be used to control power sequencing in a system with various DC-DC converters. The CT_CP_HPD pin can be connected to the output of another converter, to drive the EN pin high and getting a sequencing of supply rails. With CT_CP_HPD = GND, the DC-DC enters shutdown mode.

8.4.2 Power Save Mode

The TPD12S015A integrates a power save mode to improve efficiency at light load. In power save mode the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold voltage. The PFM mode is left and PWM mode entered in case the output current can not longer be supported in PFM mode.