TPD12S521 Single-Chip HDMI Transmitter Port Protection and Interface Device
- SLVS639F October 2007 – February 2016 TPD12S521
  
  PRODUCTION DATA.

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DATA SHEET

TPD12S521 Single-Chip HDMI Transmitter Port Protection and Interface Device

1 Features

IEC 61000-4-2 Level 4 ESD Protection
- ±8-kV Contact Discharge on External Lines
Single-Chip ESD Solution for HDMI Driver
On-Chip Current Regulator with 55-mA Current Output
Supports All HDMI 1.3 and HDMI 1.4b Data Rates
(–3 dB Frequency > 3 GHz)
0.8-pF Capacitance for the High Speed TMDS Lines
0.05-pF Matching Capacitance Between the Differential Signal Pair
38-Pin TSSOP Provides Seamless Layout Option with HDMI Connector
Backdrive Protection
- TMDS_D[2:0]+/–
- TMDS_CK+/–
- CE_REMOTE_OUT
- DDC_DAT_OUT
- DDC_CLK_OUT
- HOTPLUG_DET_OUT
Lead-Free Package

2 Applications

PCs
Consumer Electronics
Set-Top Boxes
DVD Players

3 Description

The TPD12S521 is a single-chip electro-static discharge (ESD) circuit protection device for the high-definition multimedia interface (HDMI) transmitter port. While providing ESD protection with transient voltage suppression (TVS) diodes, the TVS protection adds little or no additional glitch in the high-speed differential signals. The high-speed transition minimized differential signaling (TMDS) ESD protection lines add only 0.8-pF capacitance.

The low-speed control lines offer voltage-level shifting to eliminate the need for an external voltage level-shifter IC. The control line TVS diodes add 3.5-pF capacitance to the control lines. The 38-pin DBT package offers a seamless layout routing option to eliminate the routing glitch for the differential signal pairs. The DBT package pitch (0.5 mm) matches with the HDMI connector pitch. In addition, the pin mapping follows the same order as the HDMI connector pin mapping. The TPD12S521 provides an on-chip current limiting switch with output ratings of 55 mA at pin 38. This enables HDMI receiver detection even when the receiver device is powered off.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPD12S521	TSSOP (38)	6.40 mm × 9.70 mm

For all available packages, see the orderable addendum at the end of the datasheet.

4 Circuit Protection Scheme

5 Revision History

Changes from E Revision (February 2015) to F Revision

Add text to Typical ApplicationGo

Changes from D Revision (September 2014) to E Revision

Added clarification to HDMI data rates.Go
Added clarification to HDMI data rates.Go

Changes from C Revision (January 2013) to D Revision

Added Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go

6 Pin Configuration and Functions

Pin Functions

PIN		TYPE	ESD	DESCRIPTION
NAME	NO.	TYPE	ESD	DESCRIPTION
5V_SUPPLY	1	PWR	2 kV⁽¹⁾	Current source for 5V_OUT.
LV_SUPPLY	2	PWR	2 kV⁽¹⁾	Bias for CE/DDC/HOTPLUG level shifters.
GND, TMDS_GND	3, 5, 8, 11,14, 25, 28, 31, 34, 36	GND	NA	TMDS ESD and parasitic GND return.
TMDS_D2+	4, 35	ESD clamp	8 kV⁽²⁾	TMDS 0.8-pF ESD protection.⁽³⁾
TMDS_D2–	6, 33
TMDS_D1+	7, 32
TMDS_D1–	9, 30
TMDS_D0+	10, 29
TMDS_D0–	12, 27
TMDS_CK+	13, 26
TMDS_CK–	15, 24
CE_REMOTE_IN	16	IO	2 kV⁽¹⁾	LV_SUPPLY referenced logic level into ASIC.
DDC_CLK_IN	17
DDC_DAT_IN	18
HOTPLUG_DET_IN	19
HOTPLUG_DET_OUT	20	IO, ESD clamp	8 kV⁽²⁾	5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD⁽⁴⁾ to connector.
DDC_DAT_OUT	21			5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector.
DDC_CLK_OUT	22
CE_REMOTE_OUT	23	IO, ESD clamp	8 kV⁽²⁾	3.3-V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector.
ESD_BYP	37	ESD Bypass	2 kV⁽¹⁾	ESD bypass. This pin must be connected to a 0.1-µF ceramic capacitor.
5V_OUT	38	PWR	2 kV⁽¹⁾	5-V regulator output

(1) Human-Body Model (HBM) per MIL-STD-833, Method 3015, C_DISCHARGE = 100 pF, R_DISCHARGE = 1.5 kΩ, 5V_SUPPLY and LV_SUPPLY within recommended operating conitions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1-µF ceramic capacitor connnected to GND.

(2) Standard IEC 61000-4-2, C_DISCHARGE = 150 pF, R_DISCHARGE = 330 Ω, 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1-µF ceramic capacitor connected to GND.

(3) These two pins must be connected together inline on the PCB.

(4) This output can be connected to an external 0.1-µF ceramic capacitor, resulting in an increased ESD withstand voltage rating.

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_{5V_SUPPLY}	Supply voltage	–0.3	6	V
V_{LV_SUPPLY}	Supply voltage	–0.3	6	V
V_I/O	DC voltage at any channel input	–0.5	6	V
T_stg	Storage temperature range	–65	150	°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per MIL-STD-883, Method 3015, C_DISCHARGE = 100 pF, R_DISCHARGE = 1.5 kΩ⁽¹⁾	Pins 1, 2, 16–19, 37, 38	±2000	V
V_(ESD)	Electrostatic discharge	IEC 61000-4-2 Contact Discharge⁽²⁾	Pins 4, 7, 10, 13, 20–24, 27, 30, 33	±8000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	TYP	MAX	UNIT
T_A	Operating free-air temperature	–40		85	°C
5V_SUPPLY	Operating supply voltage		5	5.5	V
LV_SUPPLY	Bias supply voltage	1	3.3	5.5	V

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPD12S521	UNIT
		DBT
		38 PINS
R_θJA	Junction-to-ambient thermal resistance	83.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	29.8
R_θJB	Junction-to-board thermal resistance	44.7
ψ_JT	Junction-to-top characterization parameter	2.9
ψ_JB	Junction-to-board characterization parameter	44.1

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS			MIN	TYP	MAX	UNIT
I_CC5	Operating supply current	5V_SUPPLY = 5 V				110	130	µA
I_CC3	Bias supply current	LV_SUPPLY = 3.3 V				1	5	µA
V_DROP	5V_OUT overcurrent output drop	5V_SUPPLY = 5 V, I_OUT = 55 mA				150	200	mV
I_SC	5V_OUT short-circuit current limit	5V_SUPPLY= 5 V, 5V_OUT = GND			90	135	175	mA
I_OFF	OFF-state leakage current, level-shifting NFET	LV_SUPPLY = 0 V				0.1	5	µA
I_{BACK DRIVE}	Current conducted from output pins to V_SUPPLY rails when powered down	5V_SUPPLY < V_{CH_OUT}	TMDS_D[2:0]+/–, TMDS_CK+/–, CE_REMOTE_OUT, DDC_DAT_OUT, DDC_CLK_OUT, HOTPLUG_DET_OUT			0.1	5	µA
V_ON	Voltage drop across level-shifting NFET when ON	LV_SUPPLY = 2.5 V, V_S = GND, I_DS = 3 mA			75	95	140	mV
V_F	Diode forward voltage	I_F = 8 mA,	Top diode			0.85		V
V_F	Diode forward voltage	T_A = 25°C⁽¹⁾	Bottom diode			0.85		V
V_CL	Channel clamp voltage at ±8 kV HBM ESD	TA = 25°C⁽¹⁾⁽²⁾	Positive transients			9		V
V_CL	Channel clamp voltage at ±8 kV HBM ESD	TA = 25°C⁽¹⁾⁽²⁾	Negative transients			-9		V
R_DYN	Dynamic resistance	I = 1 A, T_A = 25°C⁽³⁾	Positive transients			3		Ω
R_DYN	Dynamic resistance	I = 1 A, T_A = 25°C⁽³⁾	Negative transients			1.5		Ω
I_LEAK	TMDS channel leakage current	T_A = 25°C⁽¹⁾				0.01	1	µA
C_IN, TMDS	TMDS channel input capacitance	5V_SUPPLY= 5 V, Measured at 1 MHz, V_BIAS= 2.5 V⁽¹⁾				0.8	1.0	pF
ΔC_IN, TMDS	TMDS channel input capacitance matching	5V_SUPPLY= 5 V, Measured at 1 MHz, V_BIAS= 2.5 V⁽¹⁾⁽⁴⁾				0.05		pF
C_MUTUAL	Mutual capacitance between signal pin and adjacent signal pin	5V_SUPPLY= 0 V, Measured at 1 MHz, V_BIAS= 2.5 V⁽¹⁾				0.07		pF
C_IN	Level-shifting input capacitance, capacitance to GND	5V_SUPPLY= 0 V, Measured at 100 KHz, V_BIAS= 2.5 V⁽¹⁾		DDC		3.5	4	pF
				CEC		3.5	4
				HP		3.5	4

(1) This parameter is specified by design and verified by device characterization

(2) Human-Body Model (HBM) per MIL-STD-883, Method 3015, C_DISCHARGE = 100 pF, R_DISCHARGE = 1.5 kΩ

(3) These measurements performed with no external capacitor on ESD_BYP.

(4) Intrapair matching, each TMDS pair (i.e., D+, D–)

7.6 Typical Characteristics

Figure 1. Insertion Loss Performance Across Frequency

8 Detailed Description

8.1 Overview

The TPD12S521 is a single-chip ESD solution for the HDMI transmitter port. In many cases the core ICs, such as the scalar chipset, may not have robust ESD cells to sustain system-level ESD strikes. In these cases, the TPD12S521 provides the desired system-level ESD protection, such as the IEC61000-4-2 (Level 4) ESD, by absorbing the energy associated with the ESD strike.

While providing the ESD protection, the TPD12S521 adds little or no additional glitch in the high-speed differential signals (see Figure 5 and Figure 6). The high-speed TMDS lines add only 0.8-pF capacitance to the lines. In addition, the monolithic integrated circuit technology ensures that there is excellent matching between the two-signal pair of the differential line. This is a direct advantage over discrete ESD clamp solutions where variations between two different ESD clamps may significantly degrade the differential signal quality.

The low-speed control lines offer voltage-level shifting to eliminate the need for an external voltage level-shifter IC. The control line ESD clamps add 3.5-pF capacitance to the control lines. The 38-pin DBT package offers a seamless layout routing option to eliminate the routing glitch for the differential signal pairs.

The TPD12S521 provides an on-chip regulator with current output ratings of 55 mA at pin 38. This current enables HDMI receiver detection even when the receiver device is powered off. DBT package pitch (0.5 mm) matches with HDMI connector pitch. In addition, pin mapping follows the same order as the HDMI connector pin mapping.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Single-Chip ESD Solution for HDMI Driver

TPD12S521 provides a complete ESD protection scheme for an HDMI 1.4 compliant port. The monolithic integrated circuit technology ensures that there is excellent matching between the two-signal pair of the differential line. This is a direct advantage over discrete ESD clamp solutions where variations between two different ESD clamps may significantly degrade the differential signal quality. The 38-pin DBT package offers a seamless layout routing option to eliminate the routing glitch for the differential signal pair.

8.3.2 Supports All HDMI 1.3 and HDMI 1.4b Data Rates

The high-speed TMDS pins of the TPD12S521 add only 0.8 pF of capacitance to the TMDS lines. Excellent intra-pair capacitance matching of 0.05 pF provides ultra low intra-pair skew. Insertion loss -3 dB point > 3 GHz provides enough bandwidth to pass all HDMI 1.4b TMDS data rates.

8.3.3 Integrated Level Shifting for the Control Lines

The low-speed control lines offer voltage-level shifting to eliminate the need for an external voltage level-shifter IC. The control line ESD clamps add 3.5-pF capacitance to the control lines.

8.3.4 ±8-kV Contact ESD Protection on External Lines

In many cases, the core ICs, such as the scalar chipset, may not have robust ESD cells to sustain system-level ESD strikes. In these cases, the TPD12S521 provides the desired system-level ESD protection, such as the the IEC61000-4-2 (Level 4) ESD, by absorbing the energy associated with the ESD strike.

8.3.5 38-Pin TSSOP Provides Seamless Layout Option With HDMI Connector

The 38-pin DBT package offers seamless layout routing option to eliminate the routing glitch for the differential signal pair. DBT package pitch (0.5 mm) matches with HDMI connector pitch. In addition, pin mapping follows the same order as the HDMI connector pin mapping. This HDMI receiver port protection and interface device is specifically designed for next-generation HDMI transmitter protection.

8.3.6 Backdrive Protection

Backdrive protection is offered on the following pins: TMDS_D[2:0]+/–, TMDS_CK+/–, CE_REMOTE_OUT, DDC_DAT_OUT, DDC_CLK_OUT, HOTPLUG_DET_OUT.

8.3.7 Lead-Free Package

Lead-Free Package for RoHS Compliance.

8.3.8 On-Chip Current Regulator With 55-mA Current Output

The TPD12S521 provides an on-chip regulator with current output ratings of 55 mA at pin 38. This current enables HDMI receiver detection even when the receiver device is powered off.

8.4 Device Functional Modes

TPD12S521 is active with the conditions in the Recommended Operating Conditions met. The bi-directional voltage-level translators provide non-inverting level shifting from V_LV on the system side to either 5V (for SDA , SCL, HPD), or 3.3 V (for CEC) on the connector side. Each connector side pin has an ESD clamp that triggers when voltages are above V_BR or below the lower diode's V_f. During ESD events, voltages as high as ±8-kV (contact ESD) can be directed to ground via the internal diode network. Once the voltages on the protected line fall below these trigger levels (usually within 10's of nano-seconds), these pins revert to a non-conductive state.

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

TPD12S521 provides IEC61000-4-2 Level 4 Contact ESD rating to the HDMI 1.4 transmitter port. Integrated voltage-level shifting reduces the board space needed to implement the control lines.

9.2 Typical Application

Refer to Figure 2 for a typical schematic for an HDMI 1.4 transmitter port protected with TPD12S521. The eight TMDS data lines (D2+/-, D1+/-, D0+/-, CLK+/-) each have two pins on TPD12S521 to connect to. The TMDS data lines flow through their respective pin pairs, attaching to the passive ESD protection circuitry. To block reverse current to the 3.3-V logic power rail, connect CEC_OUT to the 3.3-V logic level with a 27-kΩ pull-up resistor in series with a Schottky diode.

Figure 2. TPD12S521 Configured With an HDMI 1.4 Transmitter Port

9.2.1 Design Requirements

For this example, use the following table as input parameters:

Design Parameters	Example Value
Voltage on 5V_SUPPLY	4.5 V - 5.5 V
Voltage on LV_SUPPLY	1.7 V - 1.9 V

9.2.2 Detailed Design Procedure

To begin the design process the designer needs to know the 5V_SUPPLY voltage range and the logic level, LV_SUPPLY, voltage range.

9.2.3 Application Curves

Figure 3. HDMI 1.65Gbps Eye Diagram With TPD12S521 on a Test Board

Figure 5. Test Board to Measure Eye Diagram for the TPD12S521 (Refer to Eye Diagram Plot)

Figure 4. HDMI 1.65Gbps Eye Diagram Without TPD12S521 on a Test Board