ZHCSFE0B August 2016 – February 2022 TPD1E10B06-Q1
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 AEC-Q101 Qualified
- 7.3.2 IEC 61000-4-2 ESD Protection
- 7.3.3 ISO 10605 ESD Protection
- 7.3.4 IEC 61000-4-5 Surge Protection
- 7.3.5 IO Capacitance
- 7.3.6 Dynamic Resistance
- 7.3.7 DC Breakdown Voltage
- 7.3.8 Ultra Low Leakage Current
- 7.3.9 Clamping Voltage
- 7.3.10 Industrial Temperature Range
- 7.3.11 Space-Saving Footprint
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
6.7 Typical Characteristics
Figure 6-1 IEC 61000-4-2 Clamp Voltage +8-kV Contact ESD
Figure 6-3 Transmission Line Pulse (TLP) Waveform Pin 1 to Pin 2
Figure 6-5 IV Curve
Figure 6-7 Negative Surge Waveform (8/20 µs)
Figure 6-9 Insertion Loss
Figure 6-2 IEC 61000-4-2 Clamp Voltage –8-kV Contact ESD
Figure 6-4 Transmission Line Pulse (TLP) Waveform Pin 2 to Pin 1
Figure 6-6 Positive Surge Waveform (8/20 µs)
Figure 6-8 Pin Capacitance Across VBIAS