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SLLS684I July 2006 – March 2016 TPD2E001

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DRY|6
- MPDS221F
DRL|5
- MPDS158F
DRS|6
- MPDS176E
DZD|4
- MPDS217

散热焊盘机械数据 (封装 | 引脚)

DRY|6
- QFND138E
DRS|6
- QFND108D
DZD|4
- QFND195

订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CC	Power pin voltage		–0.3	7	V
V_IO	IO pin voltage		–0.3	V_CC + 0.3	V
T_J	Junction temperature			150	°C
	Bump temperature (soldering)	Infrared (15 s)		220	°C
	Bump temperature (soldering)	Vapor phase (60 s)		215	°C
	Lead temperature (soldering, 10 s)			300	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute-maximum-rating conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±15000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings: Surge Protection

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	IEC 61000-4-2 contact	±8000	V
V_(ESD)	Electrostatic discharge	IEC 61000-4-2 air-gap discharge	±15000	V

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
T_A, operating free-air temperature		–40	85	°C
Operating voltage	V_CC pin	0.9	5.5	V
Operating voltage	IO1, IO2 pins	0	V_CC	V

6.5 Thermal Information

THERMAL METRIC⁽¹⁾		TPD2E001				UNIT
		DRY (USON)	DRL (SOT)	DRS (WSON)	DZD (SOP)
		5 PINS	5 PINS	6 PINS	4 PINS
R_θJA	Junction-to-ambient thermal resistance	374.2	257.6	91.9	213.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	223.4	97.6	106.9	93.5	°C/W
R_θJB	Junction-to-board thermal resistance	227.8	74.2	64.8	56.8	°C/W
ψ_JT	Junction-to-top characterization parameter	52.9	7.5	10.2	4.2	°C/W
ψ_JB	Junction-to-board characterization parameter	224.8	73.7	64.9	56.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	87.5	N/A	29.9	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 Electrical Characteristics

V_CC = 5 V ± 10%, T_A = –40°C to 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP⁽¹⁾	MAX	UNIT
V_CC	Supply voltage			0.9		5.5	V
I_CC	Supply current				1	100	nA
V_F	Diode forward voltage	I_F = 10 mA		0.65		0.95	V
V_BR	Breakdown voltage	I_BR = 10 mA		11			V
V_C	Channel clamp voltage⁽²⁾	T_A = 25°C, ±15-kV HBM, I_F = 10 A	Positive transients			V_CC + 25	V
		T_A = 25°C, ±15-kV HBM, I_F = 10 A	Negative transients			–25
		T_A = 25°C, ±8-kV contact discharge (IEC 61000-4-2), I_F = 24 A	Positive transients			V_CC + 60
			Negative transients			–60
		T_A = 25°C, ±15-kV air-gap discharge (IEC 61000-4-2), I_F = 45 A	Positive transients			V_CC + 100
			Negative transients			–100
I_IO	Channel leakage current	V_I/O = GND to V_CC		–1		1	nA
C_IO	Channel input capacitance	V_CC = 5 V, bias of V_CC / 2; ƒ = 10 MHz			1.5		pF

(1) Typical values are at V_CC = 5 V and T_A = 25 °C

(2) Channel clamp voltage is not production tested.

6.7 Typical Characteristics

Figure 1. IO Capacitance vs IO Voltage (V_CC = 5 V)

Figure 3. TLP IO to GND (DRS Package)

Figure 2. IO Leakage Current vs Temperature (V_CC = 5 V)

Figure 4. TLP GND to IO (DRS Package)