10.1 Layout Guidelines

• The optimum placement of the TPD2E1B06 is as close to the connector as possible. EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. The printed-circuit board (PCB) designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces, which are between the TVS and the connector.

• Route the protected traces as straight as possible.

• Avoid sharp corners on the protected traces. Electric fields tend to build up on corners, increasing EMI coupling.

• Use thick and short traces for the ground pins

10.2 Layout Examples

Figure 13. Routing Option 1

Figure 14. Routing Option 2