9.3.1 Undervoltage Lockout (UVLO)

The UVLO circuit disables the power switch until the input voltage reaches the UVLO turn-on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large current surges.

9.3.2 Enable

The logic enable input (EN) controls the power switch, bias for the charge pump, driver, and other circuits. The supply current is reduced to less than 1 µA when the TPD3S0x4s are disabled. The enable input is compatible with both TTL and CMOS logic levels.

The turn on and turn off times (t_ON, t_OFF) are composed of a delay and a rise or fall time (t_R, t_F). The delay times are internally controlled. The rise time is controlled by both the TPD3S0x4s and the external loading (especially capacitance). TPD3S0x4s fall time is controlled by the loading (R and C), and the output discharge (R_PD). An output load consisting of only a resistor will experience a fall time set by the TPD3S0x4s. An output load with parallel R and C elements will experience a fall time determined by the (R × C) time constant if it is longer than the TPD3S0x4’s t_F. Please see Figure 25 and Figure 26 for a pictural description of t_R, t_F, t_ON, and t_OFF. The enable should not be left open; it may be tied to VIN.

Figure 25. Power-On and Power-Off Timing

Figure 26. Enable Timing, Active-High Enable

9.3.3 Internal Charge Pump

The device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel MOSFET. The charge pump supplies power to the gate driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The driver incorporates circuitry that controls the rise and fall times of the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-start functionality. The MOSFET power switch will block current from OUT to IN when turned off by the UVLO or disabled.

9.3.4 Current Limit

The TPD3S0x4s respond to overloads by limiting output current to the static current-limit (IOS) levels shown in the Electrical Characteristics: TJ = TA = 25°C table. When an overload condition is present, the device maintains a constant output current, with the output voltage determined by (I_OS × R_LOAD). Two possible overload conditions can occur.

The first overload condition occurs when either:

1. The input voltage is first applied, enable is true, and a short circuit is present (load which draws I_OUT > I_OS) or
2. The input voltage is present and the TPD3S0x4s are enabled into a short circuit.

The output voltage is held near zero potential with respect to ground and the TPD3S0x4s ramp the output current to IOS. The TPD3S0x4s will limit the current to IOS until the overload condition is removed or the device begins to thermal cycle. The device subsequently cycles current off and on as the thermal protection engages.

The second condition is when an overload occurs while the device is enabled and fully turned on. The device responds to the overload condition within t_IOS (Figure 27 and Figure 28) when the specified overload (per Electrical Characteristics table) is applied. The response speed and shape will vary with the overload level, input circuit, and rate of application. The current-limit response will vary between simply settling to I_OS, or turnoff and controlled return to I_OS. Similar to the previous case, the TPD3S0x4s will limit the current to I_OS until the overload condition is removed or the device begins to thermal cycle.

Figure 27. Output Short Circuit Parameters

Figure 28. Output Characteristic Showing Current Limit

The TPD3S0x4s thermal cycle if an overload condition is present long enough to activate thermal limiting in any of the above cases. This is due to the relatively large power dissipation [(V_IN – V_OUT) × I_OS] driving the junction temperature up. The devices turn off when the junction temperature exceeds 135°C (min) while in current limit. The devices remains off until the junction temperature cools 20°C and then restarts.

There are two kinds of current limit profiles typically available in TI switch products similar to the TPD3S0x4s. Many older designs have an output I vs V characteristic similar to the plot labeled "Current Limit with Peaking" in Figure 29. This type of limiting can be characterized by two parameters, the current limit corner (I_OC), and the short circuit current (I_OS). I_OC is often specified as a maximum value. The TPD3S0x4 parts do not present noticeable peaking in the current limit, corresponding to the characteristic labeled "Flat Current Limit" in Figure 29. This is why the I_OC parameter is not present in the Electrical Characteristics tables.

Figure 29. Current Limit Profiles

9.3.5 Output Discharge

A 470-Ω (typical) output discharge resistance will dissipate stored charge and leakage current on OUT when the TPD3S0x4s are in UVLO or disabled. The pull-down circuit will lose bias gradually as V_IN decreases, causing a rise in the discharge resistance as V_IN falls towards 0 V.

9.3.6 Input and Output Capacitance

Input and output capacitance improves the performance of the device; the actual capacitance should be optimized for the particular application. For all applications, a 0.1 µF or greater ceramic bypass capacitor between IN and GND is recommended as close to the device as possible for local noise decoupling.

All protection circuits such as the TPD3S0x4s will have the potential for input voltage overshoots and output voltage undershoots.

Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high impedance (before turn on). Theoretically, the peak voltage is 2 times the applied. The second cause is due to the abrupt reduction of output short circuit current when the TPD3S0x4s turn off and energy stored in the input inductance drives the input voltage high. Input voltage droops may also occur with large load steps and as the TPD3S0x4s outputs are shorted. Applications with large input inductance (for example, connecting the evaluation board to the bench power-supply through long cables) may require large input capacitance reduce the voltage overshoot from exceeding the absolute maximum voltage of the device. The fast current-limit speed of the TPD3S0x4s to hard output short circuits isolates the input bus from faults. However, ceramic input capacitance in the range of 1 to 22 µF adjacent to the TPD3S0x4s inputs aids in both speeding the response time and limiting the transient seen on the input power bus. Momentary input transients to 6.5 V are permitted.

Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred and the TPD3S0x4s have abruptly reduced OUT current. Energy stored in the inductance will drive the OUT voltage down and potentially negative as it discharges. Applications with large output inductance (such as from a cable) benefit from use of a high-value output capacitor to control the voltage undershoot. When implementing USB standard applications, a 120 µF minimum output capacitance is required. Typically a 150-µF electrolytic capacitor is used, which is sufficient to control voltage undershoots. However, if the application does not require 120 µF of capacitance, and there is potential to drive the output negative, a minimum of 10-µF ceramic capacitance on the output is recommended. The voltage undershoot should be controlled to less than 1.5 V for 10 µs.

9.3.7 Power Dissipation and Junction Temperature

It is good design practice to estimate power dissipation and maximum expected junction temperature of the TPD3S0x4s. The system designer can control choices of the devices proximity to other power dissipating devices and printed circuit board (PCB) design based on these calculations. These have a direct influence on maximum junction temperature. Other factors, such as airflow and maximum ambient temperature, are often determined by system considerations. It is important to remember that these calculations do not include the effects of adjacent heat sources, and enhanced or restricted air flow. Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low as practical. In particular, connect the GND pin to a large ground plane for the best thermal dissipation. The following PCB layout example Figure 30 was used to determine the R_θJA Custom thermal impedances noted in the Thermal Informationtable. It is based on the use of the JEDEC high-k circuit board construction with 4, 1 oz. copper weight layers (2 signal and 2 plane).

Figure 30. PCB Layout Example

The following procedure requires iteration because power loss is due to the internal MOSFET I² × R_DS(ON), and R_DS(ON) is a function of the junction temperature. As an initial estimate, use the R_DS(ON) at 125°C from the Typical Characteristics, and the preferred package thermal resistance for the preferred board construction from the Thermal Information table.

If the calculated T_J is substantially different from the original assumption, estimate a new value of R_DS(ON) using the typical characteristic plot and recalculate.

If the resulting T_J is not less than 125°C, try a PCB construction with a lower R_θJA. Please find the junction temperature derating curve based on the TI standard reliability duration in Figure 31.

Figure 31. Junction Temperature Derating Curve

9.4.1 Operation with V_IN < 4 V (Minimum V_IN)

These devices operate with input voltages above 4V. The maximum UVLO voltage on IN is 4V and the devices will operate at input voltages above 4 V. Any voltage below 4 V may not work with these devices. The minimum UVLO is 3.5 V, so some devices may work between 3.5 V and 4 V. At input voltages below the actual UVLO voltage, these devices will not operate.

9.4.2 Operation With EN Control

The enable rising edge threshold voltage is 1.45 V typical and 2 V maximum. With EN held below that voltage the device is disabled and the load switch will be open. The IC quiescent current is reduced in this state. When the EN pin is above its rising edge threshold and the input voltage on the IN pin is above its UVLO threshold, the device becomes active. The load switch is closed, and the current limit feature is enabled. The output voltage on OUT will ramp up with the soft start value T_ON in order to prevent large inrush current surges on V_BUS due to a heavy capacitive load. When EN voltage is lowered below is falling edge threshold, the device output voltage will also ramp down with soft turn off value T_OFF to prevent large inductive voltages being presented to the system in the case a large load current is following through the device.

9.4.3 Operation of Level 4 IEC61000-4-2 ESD Protection

Regardless of which functional mode the devices are in, TPD3S0x4 will provide Level 4 IEC61000-4-2 ESD Protection on the pins of the USB connector.