Consider the following application situations when choosing the input capacitors.

For all applications, TI recommends a 0.1-µF or greater ceramic bypass capacitor between IN and GND, placed as close as possible to the device for local noise decoupling.

During output short or hot plug-in of a capacitive load, high current flows through the TPD3S713x-Q1 device back to the upstream dc-dc converter until the TPD3S713x-Q1 device responds (after t_(IOS)). During this response time, the TPD3S713x-Q1 input capacitance and the dc-dc converter output capacitance source current to keep V_IN above the UVLO of the TPD3S713x-Q1 device and any shared circuits. Size the input capacitance for the expected transient conditions and keep the path between the TPD3S713x-Q1 device and the dc-dc converter short to help minimize voltage drops.

Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input voltage in conjunction with input power-bus inductance and input capacitance when the IN pin is in the high-impedance state (before turnon). Theoretically, the peak voltage is 2 times the applied voltage. The second cause is due to the abrupt reduction of output short-circuit current when the TPD3S713x-Q1 device turns off and energy stored in the input inductance drives the input voltage high. Applications with large input inductance (for example, a connection between the evaluation board and the bench power supply through long cables) may require large input capacitance to prevent the voltage overshoot from exceeding the absolute-maximum voltage of the device.

During the short-to-battery (EN = HIGH) condition, the input voltage follows the output voltage until OVP protection is triggered (t_{(OV_BUS)}). After the TPD3S713x-Q1 device responds and turns off the power switch, the stored energy in the input inductance can cause ringing.

Based on the three situations described, TI recommends 10-µF and 0.1-µF low-ESR ceramic capacitors, placed close to the input.