Figure 11-2 and Figure 11-3 show images from a real PCB design optimized for the best thermal performance for TPD3S716-Q1. This PCB layout has 6 layers (2 signal and 4 plane layers). The 2 signal layers are the outer layers of the PCB and constructed with 2-oz copper, and the 4 internal plane layers are constructed with 1-oz copper. Using this PCB layout yielded an R_θJA(CUSTOM) = 57 (°C/W). The images contain rough dimensions of the copper traces and pours used around the device. One key strategy to optimize thermal performance of the device is to maximize the area of the copper pours and traces used to route the device power, GND, and signal pins when possible. Another key strategy is to maximize the copper weight of the PCB metal layers. This example demonstrates that excellent thermal performance can be achieved with TPD3S716-Q1 with the proper PCB layout.

Figure 11-2 Thermally Optimized PCB Layout Top Layer

Figure 11-3 Thermally Optimized PCB Layout Bottom Layer