When the VD+, VD–, or V_{BUS_CON} pins exceed their OVP threshold, the device enters the overvoltage state. All FETs are disabled and the FLT pin is asserted. When the protected pins drop below their OVP threshold, the device automatically turns back on and deasserts the FLT pin. An overvoltage condition is only detected on an enabled path. For example, if the data path is enabled and the V_BUS path is disabled (USB Client/OTG mode), if an overvoltage condition occurs on V_{BUS_CON}, the fault pin is not be asserted. However, because the FETs of disabled paths are already turned off, proper protection from overvoltage conditions are still guaranteed by the device on disabled paths.