8.2.2 Detailed Design Procedure

When placed near the USB connectors, the TPD4E001 ESD solution offers little or no signal distortion during normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD4E001 ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper operation, the following layout/ design guidelines must be followed:

1. Place the TPD4E001 solution close to the connectors. This allows the TPD4E001 to take away the energy associated with ESD strike before it reaches the internal circuitry of the system board.
2. Place a 0.1-μF capacitor very close to the V_CC pin. This limits any momentary voltage surge at the IO pin during the ESD strike event.
3. Ensure that there is enough metallization for the V_CC and GND loop. During normal operation, the TPD4E001 consumes nA leakage current. But during the ESD event, V_CC and GND may see 15 A to
   30 A of current, depending on the ESD level. Sufficient current path enables safe discharge of all the energy associated with the ESD strike.
4. Leave the unused IO pins floating. In this example of protecting two USB ports, none of the IO pins are left unused.
5. The V_CC pin can be connected in two different ways:
   1. If the V_CC pin is connected to the system power supply, the TPD4E001 works as a transient suppressor for any signal swing above V_CC + V_F. A 0.1-μF capacitor on the device V_CC pin is recommended for ESD bypass.
   2. If the V_CC pin is not connected to the system power supply, the TPD4E001 can tolerate higher signal swing in the range up to 10 V. Please note that a 0.1-μF capacitor is still recommended at the V_CC pin for ESD bypass.