ZHCS116G May 2011 – December 2015 TPD4S014
PRODUCTION DATA.
The TPD4S014 provides a single-chip protection solution for USB charger interfaces. The VBUS line is tolerant up to 28 V DC. A Low RON nFET switch is used to disconnect the downstream circuits in case of a fault condition. At power-up, when the voltage on VBUS is rising, the switch will close 17 ms after the input crosses the under voltage threshold, thereby making power available to the downstream circuits. The TPD4S014 also has an ACK output, which de-asserts to alert the system a fault has occurred. The TPD4S014 offers 4 channel ESD clamps for D+, D-, ID, and VBUS pins that provide IEC61000-4-2 level 4 ESD protection. This eliminates the need for external TVS clamp circuits in the application.
When the input voltage rises above VOVP, or drops below the VUVLO, the internal VBUS switch is turned off, removing power to the application. The ACK signal is de-asserted when a fault condition is detected. If the fault was an over voltage event, the VBUS nFET switch turns on 8 ms (tREC) after the input voltage returns below VOVP – VHYS_OVP and remains above VUVLO. If the fault was an under voltage event, the switch turns on 17 ms after the voltage returns above VUVLO+ (similar to start up). When the switch turns on, the ACK is asserted once again.
The nFET switch has a total on resistance (RON) of 151 mΩ. This equates to a voltage drop of 302 mV when charging at the maximum 2.0 A current level. Such low RON helps provide maximum potential to the system as provided by an external charger.
The D+, D–, ID, and VBUS pins can withstand ESD events up to ±15-kV contact and air-gap. An ESD clamp diverts the current to ground.
The over voltage and under voltage lockout feature ensures that if there is a fault condition at the VBUS line, the TPD4S014 is able to isolate the VBUS line and protect the internal circuitry from damage. Due to the body diode of the nFET switch, if there is a short to ground on VBUS the system is expected to limit the current to VBUSOUT.
The D+/D– ESD protection pins have low capacitance so there is no significant impact to the signal integrity of the USB 2.0 Hi-Speed data rate.
Upon startup, TPD4S014 has a built in startup delay. An internal oscillator controls a charge pump to control the turn-on delay (tON) of the internal nFET switch. The internal oscillator controls the timers that enable the turn-on of the charge pump and sets the state of the open-drain ACK output. If VBUS < VUVLO or if VBUS > VOVLO, the internal oscillator remains off, thus disabling the charge pump. At any time, if VBUS drops below VUVLO or rises above VOVLO, ACK is released and the nFET switch is disabled.
A 17 ms deglitch time has been introduced into the turn on sequence to ensure that the input supply has stabilized before turning the nFET switch ON. Noise on the VBUS line could turn ON the nFET switch when the fault condition is still active. To avoid this, OVP glitch immunity allows noise on the VBUS line to be rejected. Such a glitch protection circuitry is also introduced in the turn off sequence in order to prevent the switch from turning off for voltage transients. The glitch protection circuitry integrates the glitch over time, allowing the OVP circuitry to trigger faster for larger voltage excursions above the OVP threshold and slower for shorter excursions.
External control of the nFET switch is provided by an active low EN pin. An ACK pin provides output logic to acknowledge VBUS is between UVLO and OVP by asserting low.
When the device is ON, current flowing through the device will cause the device to heat up. Overheating can lead to permanent damage to the device. To prevent this, an over temperature protection has been designed into the device. Whenever the junction temperature exceeds 145ºC, the switch will turn off, thereby limiting the temperature. The ACK signal will be asserted for an over temperature event. Once the device cools down to below 120ºC the ACK signal will be de-asserted, and the switch will turn on if the EN is active and the VBUS voltage is within the UVLO and OVP thresholds. While the over temperature protection in the device will not kick-in unless the die temperature reaches 145ºC, it is generally recommended that care is taken to keep the junction temperature below 125 ºC. Operation of the device above 125 ºC for extended periods of time can affect the long-term reliability of the part.
The junction temperature of the device can be calculated using below formula:
where
where
Example
At 2-A continuous current power dissipation is given by:
If the ambient temperature is about 60°C the junction temperature will be:
This implies that, at an ambient temperature of 60ºC, TPD4S014 can pass a continuous 2 A without sustaining damage. Conversely, the above calculation can also be used to calculate the total continuous current the TPD4S014 can handle at any given temperature.
Table 1 is the function table for TPD4S014.
OTP | UVLO | OVLO | EN | SW | ACK |
---|---|---|---|---|---|
X | H | X | X | OFF | H |
X | X | H | X | OFF | H |
L | L | L | H | OFF | L |
L | L | L | L | ON | L |
H | X | X | X | OFF | H |
OTP = | Over temperature protection circuit active |
UVLO = | Under voltage lock-out circuit active |
OVLO = | Over voltage lock-out circuit active |
SW = | Load switch |
CP = | Charge pump |
X = | Don’t Care |
H = | True |
L = | False |