8.1 Application Information

The TPD4S014 is a single-chip solution for USB charger port protection. This device offers low capacitance TVS type ESD clamps for the D+, D–, and standard capacitance for the ID pin. On the V_BUS pin, this device can handle over voltage protection up to 28 V. The over voltage lockout feature ensures that if there is a fault condition at the V_BUS line TPD4S014 is able to isolate the V_BUS line and protect the internal circuitry from damage. In order to let the voltage stabilize before closing the switch there is a 17 ms turn on delay after V_BUS crosses the UVLO threshold. This function acts as a de-glitch which prevents unnecessary switching if there is any ringing on the line during connection. Due to the body diode of the nFET switch, if there is a short to ground on V_BUS the system is expected to limit the current to V_BUSOUT.

8.2 Typical Applications

8.2.1 For Non-OTG USB Systems

Figure 12. Non-OTG Schematic

8.2.1.1 Design Requirements

Table 2 shows the design parameters.

Table 2. Design Parameters

DESIGN PARAMETERS	EXAMPLE VALUE
Signal range on VBUS	3.3 V – 5.9 V
Signal range on VBUSOUT	3.9 V – 5.9 V
Signal range on D+/D– and ID	0 V – 5 V
Drive EN low (enabled)	0 V – 0.5 V
Drive EN high (disabled)	1 V – 6 V

8.2.1.2 Detailed Design Procedure

To begin the design process, some parameters must be decided upon. The designer needs to know the following:

• V_BUS voltage range
• Processor logic levels V_OH, V_OL for EN and V_IH, V_IL for ACK pins

8.2.1.3 Application Curves

Figure 13. Eye Diagram With No EVM and No IC, Full USB2.0 Speed at 480 Mbps

Figure 15. Eye Diagram With EVM and IC, Full USB2.0 Speed at 480 Mbps

Figure 14. Eye Diagram With EVM, No IC, Full USB2.0 Speed at 480 Mbps

8.2.2 For OTG USB Systems

Figure 16. OTG Schematic

8.2.2.1 Design Requirements

Table 3 shows the design parameters.

Table 3. Design Parameters

DESIGN PARAMETERS	EXAMPLE VALUE
Signal range on VBUS	3.3 V – 5.9 V
Signal range on VBUSOUT	3.9 V – 5.9 V
Signal range on D+/D– and ID	0 V – 5 V
Drive EN low (enabled)	0 V – 0.5 V
Drive EN high (disabled)	1 V – 6 V

8.2.2.2 Detailed Design Procedure

To begin the design process, some parameters must be decided upon. The designer needs to know the following:

• V_BUS voltage range
• Processor logic levels V_OH, V_OL for EN and V_IH, V_IL for ACK pins
• OTG power supply output voltage range

8.2.2.3 Application Curves

Refer to Application Curves in the previous section.