11.1 Layout Guidelines

Proper routing and placement is important to maintain the signal integrity the USB2.0, SBU, CC line signals. The following guidelines apply to the TPD8S300:

• Place the bypass capacitors as close as possible to the V_PWR pin, and ESD protection capacitor as close as possible to the V_BIAS pin. Capacitors must be attached to a solid ground. This minimizes voltage disturbances during transient events such as short-to-V_BUS and ESD strikes.
• The USB2.0 and SBU lines must be routed as straight as possible and any sharp bends must be minimized.

Standard ESD recommendations apply to the C_CC1, C_CC2, C_SBU1, C_SBU2, D1, D2, D3, and D4 pins as well:

• The optimum placement for the device is as close to the connector as possible:
  • EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures.
  • The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TPD8S300 and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible.
  • Electric fields tend to build up on corners, increasing EMI coupling.
• It is best practice to not via up to the D1, D2, D3, and D4 pins from a trace routed on another layer. Rather, it is better to via the trace to the layer with the Dx pin, and to continue that trace on that same layer. See the ESD Protection Layout Guide application report, section 1.3 for more details.

11.2 Layout Example

Figure 34. TPD8S300 Typical Layout