8.3.5.1 Improved Dead Battery Performance

The TPD8S300A has improved dead battery performance over TPD8S300. In the TPD8S300 when the device is first powered (VPWR pin goes from 0V to 3.3V), the CC RD dead battery resistors are disabled at the same time the CC OVP FETs are enabled. This leads to a small ~400us time window where the CC pin can float up above the SRC.RD voltage threshold because the CC OVP FETs are still too resistive for the source to detect RD from the USB-PD controller. If the tSRCDisconnect debounce time of the USB Type-C source is less than ~400us, this could cause a USB Type-C disconnect for the source port during the dead battery boot-up event. Many USB Type-C Sources do not have a tSRCDisconnect debounce time less than ~400us; however, the USB Type-C spec allows the tSRCDisconnect time to be as low as 0ms, so some USB Type-C sources may have a tSRCDisconnect debounce time that is less than ~400us. TPD8S300A solves this problem. When the TPD8S300A is first powered (VPWR pin goes from 0V to 3.3V), TPD8S300A waits for its CC OVP FETs to be completely ON before it removes its RD dead battery resistors. This guarantees that an RD resistor will always be present on the CC line during the dead battery boot-up, and that the USB Type-C source's CC voltage will always stay in the SRC.RD range; therefore, even if a source had a tSRCDisconnect debounce time of 0ms, it will remain connected. See Figure 32 for an oscilloscope capture of TPD8S300A's proper dead battery boot-up behavior.