10.1 Layout Guidelines

To ensure reliability of the device, please follow common printed-circuit board layout guidelines.

• Leads to the input should be as direct as possible with a minimum conductor length.
• The ground path should have low resistance and low inductance.
• Short trace-lengths should be used to avoid excessive loading.
• It is common to have a dedicated ground plane on an inner layer of the board.
• Terminals that are connected to ground should have a low-impedance path to the ground plane in the form of wide polygon pours and multiple vias.
• Bypass capacitors should be used on power supplies and should be placed as close as possible to the VDD and VSS pins.
• Apply low equivalent series resistance 0.1 µF to 10 µF tantalum or electrolytic capacitors at the supplies to minimize transient disturbances and to filter low frequency ripple.
• To reduce the total I²C bus capacitance added by PCB parasitics, data lines (SCL and SDA) should be a short as possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper weight).

10.2 Layout Example

Figure 37. TPL0102 Layout Example