ZHCSE79C March   2011  – September 2015

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Operating Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Voltage Divider Mode
      3. 7.4.3 Rheostat Mode
    5. 7.5 Programming with I2C
      1. 7.5.1 I2C General Operation
        1. 7.5.1.1 I2C Interface
        2. 7.5.1.2 START and STOP Conditions
        3. 7.5.1.3 Data Validity and Byte Formation
        4. 7.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      2. 7.5.2 I2C Write and Read Operation
        1. 7.5.2.1 Auto Increment Function
        2. 7.5.2.2 Write Operation
        3. 7.5.2.3 Repeated Start
        4. 7.5.2.4 Read Operation
    6. 7.6 Register Maps
      1. 7.6.1 Slave Address
      2. 7.6.2 TPL0102 Register Map
      3. 7.6.3 IVRA (Initial Value Register for Potentiometer A)
      4. 7.6.4 WRA (Wiper Resistance Register for Potentiometer A)
      5. 7.6.5 IVRB (Initial Value Register for Potentiometer B)
      6. 7.6.6 WRB (Wiper Resistance Register for Potentiometer B)
      7. 7.6.7 ACR (Access Control Register)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Adjustable Gain Non-Inverting Amplifier
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Digital to Analog Converter (DAC)
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Variable Current Sink
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Compensation Components
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Sequence
    2. 9.2 Wiper Position Upon Power Up
    3. 9.3 Dual-Supply vs Single-Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 社区资源
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings(1)(2)(3)

MIN MAX UNIT
VDD to GND Supply voltage –0.3 7 V
VSS to GND –7 0.3 V
VDD to VSS 7 V
VH, VL, VW Voltage at resistor terminals VSS – 0.3 VDD + 0.3 V
VI Digital input voltage –0.3 VDD + 0.3 V
IH, IL, IW
Pulse current ±20 mA
Continuous current ±2 mA
Tstg Storage temperature -65 150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Single supply operation (VSS = 0 V) 2.7 5.5 V
Dual supply operation (VSS = –VDD) 2.25 2.75
VH, VL Terminal voltage range VSS VDD V
VIH Digital input voltage high (SCL, SDA, A0, A1, A2) 0.7 × VDD 5.5 V
VIL Digital input voltage low (SCL, SDA, A0, A1, A2) 0 0.3 × VDD V
IW Wiper current ±2 mA
TA Ambient temperature –40 85 °C

6.4 Thermal Information

THERMAL METRIC (1) TPL0102 UNIT
PW (TSSOP) RUC (X2QFN)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 112.9 119.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 39.9 51.3 °C/W
RθJB Junction-to-board thermal resistance 55.9 59.0 °C/W
ψJT Junction-to-top characterization parameter 3.5 1.2 °C/W
ψJB Junction-to-board characterization parameter 55.2 59.0 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

VDD = 2.7 V to 5.5 V, VSS = 0 V, VH = VDD, VL = GND, TA = –40°C to 85°C (unless otherwise noted). Typical values are at
VDD = 5 V, TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RTOT End-to-End resistance
(Between H and L Terminals)		 80 100 120 kΩ
RH, RL Terminal resistance 60 200 Ω
RW Wiper resistance 25 100 Ω
CH, CL (14) (15) Terminal capacitance 22 pF
CW (14) (15) Wiper capacitance 16 pF
ILKG Terminal leakage current VH = VSS to VDD, VL = Floating
OR
VL = VSS to VDD, VH = Floating		 0.1 1 µA
TCR Resistance temperature coefficient Input Code = 0x80h 92 ppm/°C
RTOT,MATCH Channel-to-channel resistance match 0.1 %
Voltage Divider Mode
INL(1)(3) Integral non-linearity –0.5 0.5 LSB
DNL(1)(4) Differential non-linearity –0.25 0.25 LSB
ZSERROR(2)(5) Zero-scale error 0 0.1 2 LSB
FSERROR(2)(6) Full-scale error –2 –0.1 0 LSB
MATCHVDM(2)(7) Channel-to-Channel matching Wiper at the same tap position, same voltage at all H and same voltage at all L terminals –2 2 LSB
TCVDM Ratiometric temperature coefficient Wiper set at mid-scale 4 ppm/°C
BW Bandwidth Wiper set at mid-scale
CLOAD = 10 pF		 229 kHz
tSW Wiper setting time 3.6 µs
THD Total harmonic distortion VH = 1 VRMS at 1 kHz,
VL = (VDD – VSS)/2,
Measurement at pin W		 0.03 %
XTALK Cross talk fH = 1 kHz,
VL = GND,
Measurement at pin W		 –82 dB
RHEOSTAT MODE (Measurements between W and L with H not connected, or between W and H with L not connected)
RINL(8)(10) Integral non-linearity –1 1 LSB
RDNL(8)(11) Differential non-linearity –0.5 0.5 LSB
OFFSETRM(9)(12) Offset 0 0.2 2 LSB
MATCHRM(9)(13) Channel-to-Channel matching –2 2 LSB
BW Bandwidth Code = 0x00h,
L Floating,
Input applied to W, Measure at H, CLOAD = 10 pF		 54 kHz
(1) LSB = (VMEAS[code 255] – VMEAS[code 0]) / 255
(2) IDEAL_LSB = (VH-VL) / 256
(3) INL = ((VMEAS[code x] – VMEAS[code 0]) / LSB) - [code x]
(4) DNL = ((VMEAS[code x] – VMEAS[code x-1]) / LSB) – 1
(5) ZSERROR = VMEAS[code 0] / IDEAL_LSB
(6) FSERROR = [(VMEAS[code 255] – (VH-VL)) / IDEAL_LSB] + 1
(7) MATCHVDM = (VMEAS_A[code x] – VMEAS_B[code x]) / IDEAL_LSB
(8) RLSB = (RMEAS[code 255] – RMEAS[code 0]) / 255
(9) IDEAL_RLSB = RTOT / 256
(10) RINL =( (RMEAS[code x] – RMEAS[code 0]) / RLSB) - [code x]
(11) RDNL =( (RMEAS[code x] – RMEAS[code x-1]) / RLSB )– 1
(12) OFFSETRM = RMEAS[code 0] / IDEAL_RLSB
(13) MATCHRM = (RMEAS_A[code x] – RMEAS_B[code x]) / IDEAL_RLSB
(14) Terminal and Wiper Capacitance extracted from self admittance of three port network measurement
TPL0102 fn_eq_lis135.gif
(15) Digital Potentiometer Macromodel
TPL0102 fn_pot_lis135.gif

6.6 Operating Characteristics

VDD = 2.7 V to 5.5 V, VSS = 0 V, VH = VDD, VL = GND, TA = –40°C to 85°C (unless otherwise noted). Typical values are at
VDD = 5 V, TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDD(STBY) VDD standby current VDD = 2.75 V, VSS = –2.75,
I2C interface in standby mode		 0.2 1 µA
ISS(STBY) VSS standby current VDD = 2.75 V, VSS = –2.75,
I2C interface in standby mode		 –1 –0.2 µA
IDD(SHUTDOWN) VDD shutdown current VDD = 2.75 V, VSS = –2.75,
I2C interface in standby mode		 0.2 1 µA
ISS(SHUTDOWN) VSS shutdown current VDD = 2.75 V, VSS = –2.75,
I2C interface in standby mode		 –1 –0.2 µA
IDD VDD current during non-volatile write VDD = 2.75 V, VSS = –2.75 200 µA
ISS VSS current during non-volatile write VDD = 2.75 V, VSS = –2.75 –200 µA
ILKG(DIG) Digital pins leakage current
(A0, A1, A2, SDA, and SCL)		 –1 1 µA
VPOR Power-on recall voltage Minimum VDD at which memory recall occurs 23 V
EEPROM Specification
EEPROM endurance 100 000 Cycles
EEPROM retention TA = 85°C 100 Years
tWC Non-volatile write cycle time 20 ms
Wiper Timing Characteristics
t(WRT) Wiper response time SCL falling edge of last bit of wiper data byte to wiper new position 600 ns
t(SR) Wiper position recall time from shut-down mode SCL falling edge of last bit of ACR data byte to wiper stored position and H connection 800 ns
t(D) Power-up delay VDD above VPOR, to wiper initial value register recall completed, and I2C interface in standby mode 35 100 µs
C(PIN) Pin capacitance A0, A1, A2, SDA, SCL pins 7 pF
I2C Interface Specifications
VIH Input high voltage 0.7 x VDD 5.5 V
VIL Input low voltage 0 0.3 x VDD V
VOL Output low voltage SDA pin, IOL = 4 mA 0.4 V
CIN Pin capacitance A0, A1, A2, SDA, SCL pins 7 pF

6.7 Timing Requirements

VDD = 2.7 V to 5.5 V, VSS = 0 V, VH = VDD, VL = GND, TA = –40°C to 85°C (unless otherwise noted). Typical values are at VDD = 5 V, TA = 25°C (unless otherwise noted).
STANDARD
MODE I2C BUS		 FAST
MODE I2C BUS		 UNIT
MIN MAX MIN MAX
I2C Interface Timing Requirements
fSCL I2C clock frequency 0 100 0 400 kHz
tSCH I2C clock high time 4 0.6 µs
tSCL I2C clock low time 4.7 1.3 µs
tsp I2C spike time 0 50 0 50 ns
tSDS I2C serial data setup time 250 100 ns
tSDH I2C serial data hold time 0 0 ns
tICR I2C input rise time 1000 20 + 0.1Cb(1) 300 ns
tICF I2C input fall time 300 20 + 0.1Cb(1) 300 ns
tICF I2C output fall time, 10 pF to 400 pF bus 300 20 + 0.1Cb(1) 300 ns
tBUF I2C bus free time between stop and start 4.7 1.3 µs
tSTS I2C start or repeater start condition setup time 4.7 1.3 µs
tSTH I2C start or repeater start condition hold time 4 0.6 µs
tSPS I2C stop condition setup time 4 0.6 µs
tVD(DATA) Valid data time, SCL low to SDA output valid 1 1 µs
3tVD(ACK) Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low 1 1 µs
(1) Cb = total capacitance of one bus line in pF

6.8 Typical Characteristics

TPL0102 INL_5v_code_lis134.gif
Figure 1. Voltage Divider Mode INL vs Digital Code (VDD = 5 V)
TPL0102 INL_25c_code_lis134.gif
Figure 3. Voltage Divider Mode INL vs Digital Code (25°C)
TPL0102 RINL_5v_code_lis134.gif
Figure 5. Rheostat Mode RINL vs Digital Code (VDD = 5 V)
TPL0102 RINL_25c_code_lis134.gif
Figure 7. Rheostat Mode RINL vs Digital Code (25°C)
TPL0102 TC2_code_lis134.gif
Figure 9. Rheostat Mode TCR vs Digital Code
TPL0102 FS_ta_lis134.gif
Figure 11. Voltage Divider Mode FS Error vs Temperature
TPL0102 offset_err_code_lis134.gif
Figure 13. Rheostat Mode Offset Error vs Temperature
TPL0102 res_5v_lis134.gif
Figure 15. Wiper to Low Terminal Resistance (VDD = 5 V)
TPL0102 idd_vi_lis134.gif
Figure 17. Supply Current vs Digital Input Voltage
TPL0102 DNL_5v_code_lis134.gif
Figure 2. Voltage Divider Mode DNL vs Digital Code (VDD = 5 V)
TPL0102 DNL_25c_code_lis134.gif
Figure 4. Voltage Divider Mode DNL vs Digital Code (25°C)
TPL0102 RDNL_5v_code_lis134.gif
Figure 6. Rheostat Mode RDNL vs Digital Code (VDD = 5 V)
TPL0102 RDNL_25c_code_lis134.gif
Figure 8. Rheostat Mode RDNL vs Digital Code (25°C)
TPL0102 gain2_f_lis134.gif
Figure 10. Rheostat Mode Gain vs Frequency
TPL0102 ZS_ta_lis134.gif
Figure 12. Voltage Divider Mode ZS Error vs Temperature
TPL0102 vi_t_lis134.gif
Figure 14. Midscale Wiper Glitch (0x7Fh to 0x80h)
TPL0102 res_v_lis134.gif
Figure 16. Wiper to Low Terminal Resistance (VDD = 2.7 V)
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