ZHCSQN2 December 2023 TPS1200-Q1
ADVANCE INFORMATION
When the external MOSFETs turn-OFF during the conditions such as INP1 control, overcurrent protection causing an interruption of the current flow, the input parasitic line inductance generates a positive voltage spike on the input and output parasitic inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) depends on the value of inductance in series to the input or output of the device. These transients can exceed the Section 5.1 of the device if steps are not taken to address the issue. Typical methods for addressing transients include:
The TPS12000-Q1 gets powered from the VS pin. Voltage at this pin must be maintained above V(VS_PORR) level to ensure proper operation. If the input power supply source is noisy with transients, then TI recommends to place a RVS – CVS filter between the input supply line and VS pin to filter out the supply noise. TI recommends RVS value around 100 Ω.
In case where large di/dt is involved, the system and layout parasitic inductances can generate large differential signal voltages between CS+ and CS– pins. This action can trigger false short-circuit protection and nuisance trips in the system. To overcome such scenario, TI suggests to add placeholder for RC filter components across sense resistor (RSNS) and tweak the values during test in the real system. The RC filter components must not be used in current sense designs by MOSFET VDS sensing to avoid impact on the short-circuit protection response.
The following figure shows the circuit implementation with optional protection components.