ZHCSQN2 December 2023 TPS1200-Q1
ADVANCE INFORMATION
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Parameter Measurement Information
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
- 7.3.2 Capacitive Load Driving Using FET Gate (PU, PD) Slew Rate Control
- 7.3.3 Short-Circuit Protection
- 7.3.4 Overvoltage (OV) and Undervoltage Protection (UVLO)
- 7.3.5 Reverse Polarity Protection
- 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
- 7.3.7 TPS12000-Q1 as a Simple Gate Driver
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
7.3.3.2 Short-Circuit Protection With Latch-Off
Connect an approximately 100-kΩ resistor across CTMR as shown in . With this resistor, during the charging cycle, the voltage across CTMR gets clamped to a level below V(TMR_SC) resulting in a latch-off behavior and FLT asserts low at same time.
Use Equation 8 to calculate CTMR capacitor to be connected between TMR and GND for RTMR = 100-kΩ.
Equation 8.
Where,
ITMR is internal pull-up current of 80-μA.
tSC is desired short-circuit response time.
Toggle INP or EN/UVLO (below V(ENF)) or power cycle VS below V(VS_PORF) to reset the latch. At low edge, the timer counter is reset and CTMR is discharged. PU pulls up to BST when INP is pulled high.
Figure 7-10 Short-Circuit Protection With Latch-Off