Figure 8-1 Gate Driver

Figure 8-1 shows a simplified diagram of the charge pump and gate driver circuit implementation. The device houses a strong 0.5A/2A peak source/sink gate driver (GATE) for main FETs Q1 Q2, and 100μA/0.39A peak source/sink current gate driver (G) for bypass FET Q3. The strong gate drivers enable paralleling of FETs in high power system designs ensuring minimum transition time in saturation region. A 12V in active mode, 600μA charge pump is derived from VS terminal and charges the external boot-strap capacitor, C_BST that is placed across the gate driver (BST and SRC).

VS is the supply pin to the controller. With VS applied and EN/UVLO pulled high, the charge pump turns ON and charges the C_BST capacitor. After the voltage across C_BST crosses V_{(BST_UVLOR)}, the GATE driver section is activated. The device has a 1V (typical) UVLO hysteresis to ensure chattering less performance during initial GATE turn ON. Choose C_BST based on the external FET Q_G and allowed dip during FET turn ON. In active mode, the charge pump remains enabled until the BST to SRC voltage reaches VCP_{(HIGH_AM)}, typically, at which point the charge pump is disabled decreasing the current draw on the VS pin. The charge pump remains disabled until the BST to SRC voltage discharges to VCP_{(LOW_AM)} typically at which point the charge pump is enabled.

The voltage between BST and SRC continue to charge and discharge between VCP_{(HIGH_AM)} and VCP_{(LOW_AM)} in active mode as shown in the following figure:

Figure 8-2 Charge Pump Operation

Use the following equation to calculate the initial gate driver enable delay:

Where,

C_BST is the charge pump capacitance connected across BST and SRC pins.

V_{(BST_UVLOR)} = 7.6V (typ).

If T_{DRV_EN} needs to be reduced then pre-bias BST terminal externally using an external VAUX or input supply through a low leakage diode D1 as shown in Figure 8-3. With this connection, T_{DRV_EN} reduces to 350µs.

Figure 8-3 TPS1214x-Q1 Application Circuit With External Supply to BST