During a transient output short circuit event, the current through the device increases rapidly. As the current-limit amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip comparator. The fast-trip comparator architecture is designed for fast turn OFF t_{FASTTRIP(dly)} = 1 µs (typical) with I_(SCP) = 45 A of the internal FET during an output short circuit event. The fast-trip threshold is internally set to I_(FASTTRIP). The fast-trip circuit holds the internal FET off for only a few microseconds, after which the device turns back on slowly, allowing the current-limit loop to regulate the output current to I_(OL). Then the device functions similar to the overload condition. Figure 8-5 illustrates output hot-short performance of the device.

VIN = 50 V

RILIM = 18 kΩ

Figure 8-5 Output Hot-Short Response

The fast-trip comparator architecture has a supply line noise immunity resulting in a robust performance in noisy environments. This performance is achieved by controlling the turn OFF time of the internal FET based on the overcurrent level, I_(FASTTRIP), through the device. The higher the overcurrent, the faster the turn OFF time, t_{FASTTRIP(dly)}. At Overload current level in the range of I_FASTTRIP < I_OUT < I_SCP, the fast-trip comparator response is 3.2 µs (typical).