SLVSHA1 September   2024 TPS1685

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Logic Interface
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Undervoltage Protection
      2. 7.3.2  Insertion Delay
      3. 7.3.3  Overvoltage Protection
      4. 7.3.4  Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 7.3.4.1 Slew rate (dVdt) and Inrush Current Control
          1. 7.3.4.1.1 Start-Up Time Out
        2. 7.3.4.2 Steady-State Overcurrent Protection (Circuit-Breaker)
        3. 7.3.4.3 Active Current Limiting During Start-Up
        4. 7.3.4.4 Short-Circuit Protection
      5. 7.3.5  Analog Load Current Monitor (IMON)
      6. 7.3.6  Mode Selection (MODE)
      7. 7.3.7  Parallel Device Synchronization (SWEN)
      8. 7.3.8  Stacking Multiple eFuses for Unlimited Scalability
        1. 7.3.8.1 Current Balancing During Start-Up
      9. 7.3.9  Analog Junction Temperature Monitor (TEMP)
      10. 7.3.10 Overtemperature Protection
      11. 7.3.11 Fault Response and Indication (FLT)
      12. 7.3.12 Power Good Indication (PG)
      13. 7.3.13 Output Discharge
      14. 7.3.14 FET Health Monitoring
      15. 7.3.15 Single Point Failure Mitigation
        1. 7.3.15.1 IMON Pin Single Point Failure
        2. 7.3.15.2 IREF Pin Single Point Failure
        3. 7.3.15.3 ITIMER Pin Single Point Failure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Single Device, Standalone Operation
      2. 8.1.2 Multiple Devices, Parallel Connection
    2. 8.2 Typical Application: 54V Power Path Protection in Data Center Servers
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Transient Protection
      2. 8.3.2 Output Short-Circuit Measurements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

封装选项

机械数据 (封装 | 引脚)
  • VMA|23
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.7 Timing Requirements

–40°C ≤ TJ ≤ +125°C, VIN = VDD = 45 V to 60 V, OUT = Open, RILIM = 931 Ω RIMON = 2.55 kΩ, VIREF = 1 V , FLT = 33 kΩ pull-up to 3.3 V, PGOOD = 33 kΩ pull-up to 3.3 V, COUT = 10 µF, CIN = 10 nF, dVdT = Open, ITIMER = Open. , VEN/UVLO = 2 V, TEMP = Open, MODE = Open.  (All voltages referenced to GND, (unless otherwise noted))
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tOVP Overvoltage protection response time VOVP > VOVPR V to SWEN↓  1.5 μs
tInsdly Insertion delay VEN/UVLO > VUVLO(R) to SWEN↑ 10 ms
tFFT Fixed Fast-Trip response time Hard Short VDS > VDSCOMP to IOUT↓ 195 ns
tSFT Scalable Fast-Trip response time IOUT > 3 x IOCP to IOUT↓ 400 ns
tITIMER Overcurrent blanking interval  IOUT = 1.5 x IOCP, CITIMER = Open 0 ms
tITIMER Overcurrent blanking interval  IOUT = 1.5 x IOCP, CITIMER = 4.7nF 3.5 ms
tRST Auto-Retry Interval Auto-retry variant, Primary mode (MODE = Open) 285 ms
tREC Fault Recovery Time Secondary mode (MODE = GND), SWEN↓ to SWEN↑ 12 μs
tEN(DG) EN/UVLO de-glitch time 13 μs
tSWEN(TO) SWEN low interval to disable fast recovery us
tSU_TMR Start-up timeout interval SWEN↑ to FLT↓   5 s
tDischarge QOD discharge time (90% to 10% of VOUT) VSD < VEN/UVLO < VUVLO, COUT = 0.5 mF, VIN = 51 V.  1300 ms
tQOD QOD enable timer VSD < VEN/UVLO < VUVLO 6 ms
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