11.1 Layout Guidelines

• For best performance, all traces should be as short as possible.
• To be most effective, the input and output capacitors should be placed close to the device to minimize the effects that parasitic trace inductances may have on normal and short-circuit operation.
• The V_IN terminal should be bypassed to grond with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is 1-µF ceramic with X5R or X7R dielectric. This capacitor should be placed as close to the device terminals as possible.
• The V_OUT terminal should be bypassed to grond with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is one-tenth of the VIN bypass capacitor of X5R or X7R dielectric. This capacitor should be placed as close to the device terminals as possible.
• Using wide traces for V_IN, V_OUT, and GND will help minimize parasitic electrical effects along with minimizing the case to ambient thermal impedance.

11.2 Layout Example

11.3 Thermal Considerations

The maximum junction temperature will be internally limited by the thermal shutdown (T_SD). To calculate the maximum allowable dissipation, P_D(MAX) for a given ambient temperature, use Equation 5.

Equation 5.

where

• P_D(MAX) = maximum allowable power dissipation
• T_SD = thermal shutdown threshold (140 °C typical)
• T_A = ambient temperature of the device
• θ_JA = junction to air thermal impedance. See the section. This parameter is highly dependent upon board layout.