10.1.1 Input to OutputVoltage Drop

The input to output voltage drop in the device is determined by the R_ON of the device and the load current. The R_ON of the device depends upon the V_IN and V_BIAS conditions of the device. Refer to the R_ON specification of the device in the Electrical Characteristics table of this datasheet. Once the R_ON of the device is determined based upon the V_IN and V_BIAS voltage conditions, use Equation 5 to calculate the input to output voltage drop:

Equation 5.

Where:

ΔV = voltage drop from IN to OUT
I_LOAD = load current
R_ON = On-Resistance of the device for a specific V_IN and V_BIAS

An appropriate I_LOAD must be chosen such that the I_MAX specification of the device is not violated.

10.1.2 Thermal Considerations

The maximum IC junction temperature should be restricted to just under the thermal shutdown (T_SD) limit of the device. To calculate the maximum allowable dissipation, P_D(max) for a given output current and ambient temperature, use Equation 6.

Equation 6.

Where:

P_D(max) = maximum allowable power dissipation
T_J(max) = maximum allowable junction temperature before hitting thermal shutdown (see Electrical Characteristics table)
T_A = ambient temperature of the device
θ_JA = junction to air thermal impedance. See Thermal Information section. This parameter is highly dependent upon board layout.

10.1.3 Automatic Power Sequencing

The PG pin of the TPS22953/54 allows for automatic sequencing of multiple system rails or loads. The accurate SNS voltage monitoring will ensure the first rail is up before the next starts to turn on. This approach provides robust system sequencing and reduces the total inrush current by preventing overlap. The example shows how two rails can be sequenced. There is no limit to the number of rails that can be sequenced in this way

Figure 55. Power Sequencing with PG Control

10.1.4 Monitoring a Downstream Voltage

The SNS pin can be used to monitor other system voltages in addition to V_OUT. The status of the monitored voltage will be indicated by the PG pin which can be pulled up to V_OUT or another voltage. The figure below shows an example of the TPS22953/54 monitoring the output of a downstream DC/DC regulator. In this case, the switch will turn on when the power supply is above the UVLO, but the PG will not be asserted until the DC/DC regulator has started up.

Figure 56. Monitoring a Downstream Voltage

In this application, if the DC/DC Regulator is shut down, the supervisor will register this as a fault case and reset the load switch.

10.2.1 Design Requirements

For this design example, use the following as the input parameters.

10.2.2 Detailed Design Procedure

To begin the design process, the designer needs to know the following:

• Input voltage
• BIAS voltage
• Load current
• Load capacitance
• Maximum acceptable inrush current

10.2.2.1 Inrush Current

To determine how much inrush current will be caused by the C_L capacitor, use Equation 7:

Equation 7.

Where:

I_INRUSH = amount of inrush caused by C_L
C_L = capacitance on V_OUT
dt = V_OUT Rise Time (typically 10% to 90%)
dV_OUT = Change in V_OUT Voltage (typically 10% to 90%)

In this case, a Slew Rate slower than 314μs/V will be required to meet the maximum acceptable inrush requirement. Equation 4 can be used to estimate the CT capacitance required for this slew rate.

10.2.3 Application Curves

The following Application Curves show the inrush with multiple different CT values. These curves show only a CT capacitance greater than 840pF results in the acceptable inrush current of 150mA.

CT = 0 pF

Figure 59. Inrush with CT = 0 pF

CT = 470 pF

Figure 61. Inrush with CT = 470 pF

CT = 2200 pF

Figure 63. Inrush with CT = 2200 pF

CT = 220 pF

Figure 60. Inrush with CT = 220 pF

CT = 1000 pF

Figure 62. Inrush with CT = 1000 pF