ZHCSDK9A March 2015 – April 2015 TPS22953 , TPS22954
PRODUCTION DATA.
PIN(1) | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
IN | 1, 2 | I | Switch input. Bypass this input with a ceramic capacitor to GND. |
BIAS | 3 | I | Bias pin and power supply to the device. |
EN | 4 | I | Active high switch enable/disable input. Also acts as the input UVLO pin. Use external resistor divider to adjust the UVLO level. Do not leave floating. |
GND | 5 | – | Device ground. |
CT | 6 | O | VOUT slew rate control. Place ceramic cap from CT to GND to change the VOUT slew rate of the device and limit the inrush current. CT Capacitor should be rated to 25V or higher. |
PG | 7 | O | Power good. This pin is open drain which will pull low when the voltage on EN and/or SNS is below their respective VIL level. |
SNS | 8 | I | Sense pin. Use external resistor divider to adjust the power good level. Do not leave floating. |
OUT | 9, 10 | O | Switch output. |
Thermal Pad | – | – | Exposed thermal pad. Tie to GND. |