The PG pin is only asserted high when the voltage on EN exceeds V_IH,EN and the voltage on SNS exceeds V_IH,SNS. There is a t_BLANK time, typically 100 µs, between the SNS voltage exceeding V_IH,SNS and PG being asserted high. If the voltage on EN goes below V_IL,EN or the voltage on SNS goes below V_IL,SNS, PG is de-asserted. There is a t_DEGLITCH time, typically 5 µs, between the EN voltage or SNS voltage going below their respective V_IL levels and PG being pulled low.

PG is an open drain pin and must be pulled up with a pullup resistor. Be sure to never exceed the maximum operating voltage on this pin. If PG is not being used in the application, tie it to GND for proper device functionality.

For proper PG operation, the BIAS voltage must be within the recommended operating range. In systems that are very sensitive to noise or have long PG traces, TI recommends to add a small capacitance from PG to GND for decoupling.