11.1 Layout Guidelines

• VIN and VOUT traces should be as short and wide as possible to accommodate for high current.
• Use vias under the exposed thermal pad for thermal relief for high current operation.
• The VIN pin should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is 1-µF ceramic with X5R or X7R dielectric. This capacitor should be placed as close to the device pins as possible.
• The VOUT pin should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is one-tenth of the VIN bypass capacitor of X5R or X7R dielectric rating. This capacitor should be placed as close to the device pins as possible.
• The VBIAS pin should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is 0.1-µF ceramic with X5R or X7R dielectric.

11.2 Layout Example

Figure 42. Recommended Board Layout