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ZHCSCN4F January 2014 – July 2017 TPS22968

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DPU|14
- MPSS042A

散热焊盘机械数据 (封装 | 引脚)

DPU|14
- QFND320

订购信息

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

This section highlights some of the design considerations for implementing this device in various applications. A PSPICE model for this device is also available on the product page for additional information.

10.1.1 Parallel Configuration

To increase the current capabilities and lower the R_ON by approximately 50%, both channels can be placed in parallel as shown in Figure 31 (parallel configuration). With this configuration, the CT1 and CT2 pins can be tied together to use one capacitor, CT, as shown in Figure 31. With a single CT capacitor, the rise time is half of the typical rise-time value. Refer to the Table 1 for typical timing values.

TPS22968 TPS22968N paracon_shared_lvscg3.gif

Figure 31. Parallel Configuration

10.1.2 Standby Power Reduction

Any end equipment that is powered from the battery has a need to reduce current consumption to keep the battery charged for a longer time. TPS22968 helps to accomplish this by turning off the supply to the modules that are in standby state, and therefore, significantly reduces the leakage current overhead of the standby modules. See Figure 32.

TPS22968 TPS22968N std_pwr_red_lvscg3.gif

Figure 32. Standby Power Reduction

10.1.3 Power Supply Sequencing Without a GPIO Input

In many end equipments, there is a need to power up various modules in a predetermined manner. The TPS22968 can solve the problem of power sequencing without adding any complexity to the overall system. See Figure 33.

TPS22968 TPS22968N pwr_seq_without_lvscg3.gif

VIN1 must be greater V_IH.

Figure 33. Power Sequencing Without a GPIO Input

10.1.4 Reverse Current Blocking

In certain applications, it may be desirable to have reverse current blocking. Reverse current blocking prevents current from flowing from the output to the input of the load switch when the device is disabled. With the following configuration, the TPS22968 can be converted into a single-channel switch with reverse current blocking. In this configuration, VIN1 or VIN2 can be used as the input and VIN2 or VIN1 is the output. See Figure 34.

TPS22968 TPS22968N reverse_cur_blk_lvscg3.gif

Figure 34. Reverse Current Blocking

10.2 Typical Application

This application demonstrates how the TPS22968 can be used to power downstream modules with large capacitances. The example in Figure 35 TPS22968 is powering a 100-µF capacitive output load.

TPS22968 TPS22968N typicalApplication_SLVSG3.gif

Figure 35. Typical Application Schematic for Powering a Downstream Module

10.2.1 Design Requirements

For this design example, use the following Table 3 as the input parameters.

Table 3. Design Parameters

DESIGN PARAMETER	EXAMPLE VALUE
V_IN	3.3 V
V_BIAS	5 V
Load current	4 A
Output capacitance (C_L)	22 µF
Allowable inrush current on VOUT	0.33 A

10.2.2 Detailed Design Procedure

To begin the design process, the designer must know the following:

V_IN voltage
V_BIASvoltage
Load current
Allowable inrush current on VOUT due to C_L capacitor

10.2.2.1 VIN to VOUT Voltage Drop

The VIN to VOUT voltage drop in the device is determined by the R_ON of the device and the load current. The R_ON of the device depends upon the V_IN and V_BIAS conditions of the device. Refer to the R_ON specification of the device in the Electrical Characteristics (VBIAS = 5 V) and Electrical Characteristics (VBIAS = 2.5 V) . After the R_ON of the device is determined based upon the V_IN and V_BIAS conditions, use Equation 2 to calculate the VIN to VOUT voltage drop:

Equation 2. TPS22968 TPS22968N eq1_delta_slvsci4.gif

where

ΔV is the voltage drop from VIN to VOUT
I_LOAD is the load current
R_ON is the On-resistance of the device for a specific V_IN and V_BIAS combination

An appropriate I_LOAD must be chosen such that the I_MAX specification of the device is not violated.

10.2.2.2 Inrush Current

To determine how much inrush current is caused by the C_L capacitor, use Equation 3.

Equation 3. TPS22968 TPS22968N Eq2_Iinrush_slvsci4.gif

where

I_INRUSH is the amount of inrush caused by C_L
C_L is the capacitance on VOUT
dt is the time it takes for change in V_OUT during the ramp up of VOUT when the device is enabled
dV_OUT is the change in V_OUT during the ramp up of VOUT when the device is enabled

The device offers adjustable rise time for VOUT. This feature allows the user to control the inrush current during turnon through the CTx pins. The appropriate rise time can be calculated using the design requirements and the inrush current equation ( Equation 3). See Equation 4 and Equation 5.

Equation 4. 330 mA = 22 µF × 3.3 V / dt

Equation 5. dt = 220 µs

To ensure an inrush current of less than 330 mA, choose a CT based on Table 1 or Equation 1 value that yields a rise time of more than 220 µs. See the oscilloscope captures in the Application Curves for an example of how the CT capacitor can be used to reduce inrush current. See Table 1 for correlation between rise times and CT values.

An appropriate C_L value must be placed on VOUT such that the I_MAX and I_PLS specifications of the device are not violated.

10.2.2.3 Thermal Considerations

The maximum IC junction temperature must be restricted to 125°C under normal operating conditions. To calculate the maximum allowable dissipation, P_D(max) for a given output current and ambient temperature, use Equation 6.

Equation 6. TPS22968 TPS22968N eq_thrm_slvsci4.gif

where

P_D(max) is the maximum allowable power dissipation
T_J(max) is the maximum allowable junction temperature (125°C for the TPS22968)
T_A is the ambient temperature of the device
R_θJA is the junction to air thermal impedance. See the Thermal Information table. This parameter is highly dependent upon board layout.

Equation 7 to Equation 10 and Equation 11 to Equation 13 show two examples to determine how to use this information correctly:

For V_BIAS = 5 V, V_IN = 5 V, the maximum ambient temperature with a 4-A load through each channel can be determined by using Equation 7 to Equation 10:

White Space

Equation 7. P_D = I² × R × 2 (multiplied by 2 because there are two channels)

White Space

Equation 8. TPS22968 TPS22968N temp_eq1b_lvscg3.gif

White Space

Equation 9. T_A = T_J(MAX) – R_θJA × 2 × I² × R

White Space

Equation 10. T_A = 125°C – 62.5°C/W × 2 × (4 A)² × 27 mΩ = 71°C

White Space

For V_BIAS = 5 V, V_IN = 5 V, the maximum continuous current for an ambient temperature of 85°C with the same current flowing through each channel can be determined by using Equation 11 to Equation 13:

Space

Equation 11. TPS22968 TPS22968N temp_eq2a_lvscg3.gif

Space

Equation 12. TPS22968 TPS22968N temp_eq2b_lvscg3.gif

Space

Equation 13. TPS22968 TPS22968N temp_eq2c_lvscg3.gif

10.2.3 Application Curves

The twp scope captures show the usage of a CT capacitor in conjunction with the device. A higher CT value results in a slower rise and a lower inrush current.

TPS22968 TPS22968N tps22968_inrush_vin_3p3v_CL_22uF_Ct_0.gif

VBIAS = 5 V	VIN = 3.3 V	T_A = 25°C
CT = Open

Figure 36. Inrush Current Without CT Capacitor

TPS22968 TPS22968N tps22968_inrush_vin_3p3v_CL_22uF_Ct_220pF.gif

VBIAS = 5 V	VIN = 3.3 V	T_A = 25°C
CT = 220 pF

Figure 37. Inrush Current With CT = 220 pF