ZHCSHW5A September   2017  – December 2017 TPS23521

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化原理图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Relationship between Sense Voltage, Gate Current, and Timer
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Current Limit
        1. 8.3.1.1 Programming the CL Switch-Over Threshold
        2. 8.3.1.2 Setting Up the PROG Pin
        3. 8.3.1.3 Programming CL1
        4. 8.3.1.4 Programming CL2
      2. 8.3.2 Soft Start Disconnect
      3. 8.3.3 Timer
      4. 8.3.4 Gate 2
    4. 8.4 Device Functional Modes
      1. 8.4.1 OFF State
      2. 8.4.2 Insertion Delay State
      3. 8.4.3 Start-up State
      4. 8.4.4 Normal Operation State
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting RSNS
        2. 9.2.2.2 Selecting Soft Start Setting: CSS and CSS,VEE
        3. 9.2.2.3 Selecting VDS Switch Over Threshold
        4. 9.2.2.4 Timer Selection
        5. 9.2.2.5 MOSFET Selection and SOA Checks
        6. 9.2.2.6 EMI Filter Consideration
        7. 9.2.2.7 Under Voltage and Over Voltage Settings
        8. 9.2.2.8 Choosing RVCC and CVCC
        9. 9.2.2.9 Power Good Interface to Downstream DC/DC
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

MOSFET Selection and SOA Checks

When selecting MOSFETs for the –48 V application the three key parameters are: VDS rating, RDSON, and safe operating area (SOA). For this application the PSMN4R8-100BSE was selected as the Main hot swap FET (Q1) to provide a 100 V VDS rating, low RDSON, and great SOA. Since this is a high power application 2 CSD19532Q5B FETs were used as auxiliary FETs (Q2) to reduce steady state power dissipation. After selecting the MOSFET, it is important to double check that it has sufficient SOA to handle the key stress scenarios: start-up, output Hot Short, and Start into Short. MOSFET's SOA is usually specified at a case temperature of 25°C and should be derated based on the maximum case temperature expected in the application.

First, compute how much current will flow through Q1 using a current division formula shown below. For this example the FET RDSON at 100°C was used. RDSON of Q1 (RDSON1) is 4.8 mΩ (PSMNR8-100BSE max RDSON at 25°C) x 1.8 (temperature coefficient), which equals 8.64 mΩ. RDSON of Q2 (RDSON2) is 4.9 mΩ (CSD19532Q5B max RDSON at 25°C) x 1.6 (temperature coefficient), which equals 7.84 mΩ.

Equation 17. TPS23521 tps23521_equation7.gif

Next the maximum temperature of Q1 can be computed using the equations below.

Equation 18. TPS23521 tps23521_equation8.gif
Equation 19. TPS23521 tps23521_equation9.gif

Next the stress the MOSFET will experience during operation should be compared to the FETs capability. First, consider the power up. The inrush current with max COUT will be 0.53 A and the inrush will last for 198 ms. Note that the power dissipation of the FET will start at VIN,MAX × IINR and reduce to zero as the VDS of the MOSFET is reduced. The SOA curve of a typical MOSFET assume the same power dissipation for a given time. A conservative approach is to assume an equivalent power profile where PFET = VIN,MAX × IINR for t = Tstart-up /2. In this instance, the SOA can be checked by looking at a 72 V, 0.53 A, 99 ms pulse. Based on the SOA of the PSMN4R8-100BSE, it can handle 72 V, 3 A for 10 ms and it can handle 72 V, 1.3 A for 100 ms. The SOA at TC = 25°C for 99 ms can be extrapolated by approximating SOA vs time as a power function as shown in equations below:

Equation 20. TPS23521 tps23523_equation19.gif
Equation 21. TPS23521 tps23521_equation10.gif
Equation 22. TPS23521 tps23521_equation11.gif
Equation 23. TPS23521 tps23521_equation12.gif

Finally, the FET SOA needs to be derated based on the maximum case temperature as shown below. Note that the FET can handle 0.79 A, while it will have 0.53 A during start-up. Thus there is a lot of margin during this test condition.

Equation 24. TPS23521 tps23521_equation13.gif

A similar approach should be taken to compute the FETs SOA capability during a Hot Short and start into short. As shown in the following figure, during a start into short the gate is coming up very slowly due to a large capacitance tied to the gate through the SS pin. Thus it is more stressful than a Hot Short and should be used for worst case SOA calculations. To compare the FET stress during start-up into short to the SOA curves the stress needs to be approximated as a square pulse as showing in the figure below. In this example, the stress is approximated with a 1.3 ms (Teq), 3 A, 72 V pulse. The FET can handle 18 A, 72 V for 1 ms and 3 A, 72 V for 10 ms. Using approximation and temp derating as shown earlier, the FET's capability can be computed as 8.9 A, 72 V, for 1.3 ms at 83.7°C. 8.9 A is significantly larger than 3 A implying great margin.

TPS23521 StartIntoShort_TPS23521_EVM.pngFigure 13. Teq During a Start Into a Short

The final operating point to check is the operation with high current and VDS just below the VDS,SW threshold. In this example, the time out would be 1.1ms (one half of the time out at Vd = 0 V), the current will be 40 A, and the voltage would be 20 V. Looking up the SOA curve, the FET can handle 100 A, 20 V for 1 ms and 40 A, 20 V for 10 ms. Repeating previously shown approximations and temp derating, the FET's capability is computed to be 58 A, 20 V, for 1.1 ms at 83.7°C. Again this is below the worst case operating point of 40 A and 20 V suggesting good margin.