ZHCSGZ0B October   2017  – November 2017 TPS23525

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化电路原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Relationship between Sense Voltage, Gate Current, and Timer
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Current Limit
        1. 8.3.1.1 Programming the CL Switch-Over Threshold
        2. 8.3.1.2 Programming CL1
        3. 8.3.1.3 Programming CL2
        4. 8.3.1.4 Computing the Fast Trip Threshold
      2. 8.3.2 Soft Start Disconnect
      3. 8.3.3 Timer
      4. 8.3.4 OR-ing
    4. 8.4 Device Functional Modes
      1. 8.4.1 OFF State
      2. 8.4.2 Insertion Delay State
      3. 8.4.3 Start-up State
      4. 8.4.4 Normal Operation State
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Selecting RSNS
        2. 9.2.2.2  Selecting Soft Start Setting: CSS and CSS,VEE
        3. 9.2.2.3  Selecting VDS Switch Over Threshold
        4. 9.2.2.4  Timer Selection
        5. 9.2.2.5  MOSFET Selection and SOA Checks
        6. 9.2.2.6  Input Cap, Input TVS, and OR-ing FET selection
        7. 9.2.2.7  EMI Filter Consideration
        8. 9.2.2.8  Under Voltage and Over Voltage Settings
        9. 9.2.2.9  Choosing RVCC and CVCC
        10. 9.2.2.10 Power Good Interface to Downstream DC/DC
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

–40°C ≤ TJ ≤125°C, 1.1 mA < IVCC< 10 mA, V(UVEN) = 2 V, V(OV) = V(SNS) = V(D) = 0 V, V(SS) = GATEx = Hi-Z , V(TMR) = 0 V, –1 V < VNEG48Vx< 150 V, ; All pin voltages are relative to VEE (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC – Clamped Supply
V(UVLO_VCC) UVLO on VCC rising 9 9.5 10 V
V(UVLO_VCC,hyst) UVLO hysteresis on VCC hysteresis 1 V
V(VCC) VCC regulation 1.1< I(VCC)< 10 mA (current into VCC) 12 14.5 18 V
IQ Quiescent Current VVCC = 10 V. Off 1 mA
VVCC = 10 V. On 1 mA
VVCC = 10 V, Gate, GATEA, GATEB in regulation 1.1 mA
UVEN – Under Voltage and Enable
V(UVEN_T) Threshold voltage for V(UVEN) 0.985 1 1.015 V
I(UV_hyst) Hysteresis current, sourcing from UV pin VUV = 1.5 V 9 10 11.2 µA
OV – Over Voltage
V(OV_T) Threshold voltage for VOV 0.98 1 1.02 V
I(OV_hyst) Hysteresis current, sourcing from OV pin VOV = 1.5 V 9 10 11.2 µA
TMR – Timer
VTMR Voltage on timer when part times out. VD = 0 V, TMR ↑, measure VTMR when VGATE = 0 1.47 1.5 1.53 V
VTMR2 Voltage on timer when part times out. VD = 1 V, TMR ↑, measure VTMR when VGATE = 0 0.735 0.75 0.765 V
ITMR,SRs Timer Sourcing current when in fault condition or when retrying. VSNS = 0.1 V, VD = 0 V, VTMR = 0 V, measure I out from TMR 9 10 11 µA
VSNS = 0.1 V, VD = 2 V, VTMR = 0 V, measure I out from TMR 45 50 55 µA
ITMR,SNC Timer sinking current when not in fault condition. VSNS = 0 V, VD = 0 V, VTMR = 2 V, 1.5 2 2.5 µA
VTMR,RETRY Voltage on timer when the timer starts going back up in retry. Retry version only. VSNS = 0 V, VD = 0 V, TMR ↑ = 2 V, TMR ↓, measure VTMR when I into TMR change polarity 0.475 0.5 0.525 V
NRETRY Number of retry duty cycles. Retry version only. 64
DRETRY Retry duty cycle. Retry version only. 0.4%
IGATE,TIMER Gate Sourcing Current Threshold When timer starts to run. VG = 5 V, VD = 2 V, VSNS ↑, measure IGATE when TMR sources current 5 10 15 µA
VSNS,TMR1 Sense Voltage when Timer starts to run. VD = 2 V, VTMR = 0 V, VG = 5 V; VSNS ↑, measure VSNS when TMR sources current 1.5 2.5 mV
VSNS,TMR2 Sense Voltage when Timer starts to run. VD = 0 V, VTMR = 0 V , VG = 5 V; VSNS ↑, measure VSNS when TMR sources current 23.25 24.5 mV
SNS – Sense Pin For Current Limit
ISNS,LEAK Leakage current on sense pin -2 2 µA
VSNS,CL1 Current limit VTMR = 0 V. VGATE = 5 V. VD = 0 V VSNS ↑, measure when IGATE = 0; 24 25 26 mV
VSNS,FST fast trip current limit VTMR = 0 V. VGATE = 5 V. VD = 0 V. VSNS ↑, measure when IGATE> 100 mA 45 50 55 mV
VSNS,CL2 Fold Back Current Limit VTMR = 0 V, VGATE = 5 V, VD = 5 V, VSNS ↑, measure when IGATE = 0; 2.25 3 3.75 mV
VSNS,FST2 Fast Trip during start-up VTMR = 0 V, VGATE = 5 V, VD = 5 V, VSNS ↑, Measure when IGATE> 100 mA 6 9 12 mV
GATE – Gate Drive for Main Hot Swap FET
V(VCC-GATE) Output gate voltage V(SNS) = 0 V 1 V
I(GATE,SRS,NORM) Sourcing Current during normal operation. V(TMR) = 0 V. V(GATE) = 8 V. VD = 0 V, V(SNS) = 0 V 250 400 µA
I(GATE,SRS,START) Sourcing Current during star-up V(TMR) = 0 V. V(GATE) = 5 V. VD = 0 V, V(SNS) = 0 V 15 20 25 µA
I(GATE,wkpd) Weak pull down current V(SNS) = 0 V. VUVEN = 0 V 3 5 7 mA
I(GATE,FST) Fast Pull down current with 10mV overdrive 0.4 1 1.5 A
D – Drain Sense
R(D,INT) Resistance from the drain pin to GND. 28.5 30 31.5 kΩ
V(D,CL_SW) Voltage on drain that switches between two current limits V(TMR) = 0 V, V(GATE) = 5 V, V(SNS) = 20 mV, D↑, measure V when I(GATE) = 0 1.46 1.5 1.54 V
V(D,TMR_SW) Voltage on drain that switches the VTMR threshold. V(TMR) = 1 V, V(GATE) = 5 V, V(SNS) = 20 mV, D↑, measure V when I(GATE) = 0 0.73 0.75 0.77 V
V(D,TMR_SW,hyst) hysteresis for V(D,TMR,SW) hysteresis 75 mV
SS (Soft Start)
I(SS,PD) Pull down current when not in inrush VSS = 5 V 100 mA
R(SS,GATE) Resistance between GATE and SS in the start-up phase 80 Ω
Neg48A, Neg48B
I(lkg,Neg48x) Leakage current VNeg48x = –50 mV, GATEx ON -2 2 µA
VNeg48x = –100 mV, GATEx ON -7 7 µA
VNeg48x = 150 V, GATEx off 30 µA
V(FWD) Forward regulation voltage of the OR-ing controller. VFWD = VEE – V(NEG48Vx) 10 25 40 mV
V(FWD,FST) Forward voltage where a fast pull up is activated. VGATEx = 5 V. VVEE – VNeg48Vx ↑ measure when IGATEx = 100 µA 50 80 105 mV
V(RV) Fast reverse trip voltage. 2 6 10 mV
GATEA, GATEB
VVCC-GATEx Gate Output Voltage. 0.65 1.1 V
I(GATEx,SRS) Gate sourcing current in regulation VVEE – VNeg48Vx = 50 mV 5 µA
I(GATEx,SINK) Gate sinking current in regulation VVEE – VNeg48Vx = 0 5 µA
RGATE,SRC,FST Pull up resistance in fast sourcing mode. VVEE – VNeg48Vx = 100 mV; Measure current at VGATEx = 0 V. R = VVCC/I 10 kΩ
I(GATEx,FST) Fast Gate pull down current V(VEE) – VNeg48x = –15 mV 0.4 1 1.5 A
PGb (Power Good Bar)
V(GATE,PGb) Threshold on GATE that triggers PGb to assert. Raise VGATE until PGb asserts 6.5 7.25 8 V
V(PGb,PD) Pull down strength on PGb PGb sinking 1 mA 1.5 V
I(PGb,LEAK) leakage current on PGb pin 1 µA
OTSD (Over Temperature Shut Down)
TSD Shutdown temperature Temp Rising 135 155 175 °C
TSD,hyst Shutdown temperature Hysteresis 8 °C
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