CTL is the voltage control loop input to the PWM (pulse width modulator). Pulling V_CTL below V_ZDC causes GATE to stop switching. Increasing V_CTL above V_ZDC raises the switching MOSFET programmed peak current. The maximum (peak) current is requested at approximately V_ZDC + (2 × V_CSMAX). The AC gain from CTL to the PWM comparator is 0.5.

Use V_B as a pullup source for CTL.