ZHCSMU0D July 2009 – December 2020 TPS23753A
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Product Information
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4
Device Functional Modes
- 8.4.1 Threshold Voltages
- 8.4.2 PoE Start-Up Sequence
- 8.4.3 Detection
- 8.4.4 Hardware Classification
- 8.4.5 Maintain Power Signature (MPS)
- 8.4.6 TPS23753A Operation
- 8.4.7 Special Switching MOSFET Considerations
- 8.4.8 Thermal Considerations
- 8.4.9 FRS and Synchronization
- 8.4.10 Blanking – RBLNK
- 8.4.11 Current Slope Compensation
- 8.4.12 Adapter ORing
- 8.4.13 Protection
- 8.4.14 Frequency Dithering for Conducted Emissions Control
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.4.2 PoE Start-Up Sequence
The waveforms of Figure 8-3 demonstrate detection, classification, and start-up from a Type 1 PSE. The key waveforms shown are VVDD-VSS, VRTN-VSS, and IPI. IEEE 802.3at requires a minimum of two detection levels; however, four levels are shown in this example. Four levels guard against misdetection of a device when plugged in during the detection sequence.
Figure 8-3 PoE Start-Up Sequence