The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and classification. The converter circuits discharges C_IN, C_VC, and C_VB while the PD is unpowered. Thus V_RTN-VDD will be a small voltage just after full voltage is applied to the PD, as seen in Figure 8-3.

The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When V_DD rises above the UVLO turnon threshold (V_UVLO-R, approximately 35 V) with RTN high, the TPS23753A enables the hotswap MOSFET with an approximately 140-mA (inrush) current limit. See the waveforms of Figure 8-4 for an example. Converter switching is disabled while C_IN charges and V_RTN falls from V_DD to nearly V_SS; however, the converter start-up circuit is allowed to charge C_VC. Once the inrush current falls about 10% below the inrush current limit, the PD control switches to the operational level (approximately 450 mA) and converter switching is permitted.

Converter switching is allowed if the PD is not in inrush and the V_C UVLO circuit permits it. Continuing the start-up sequence shown in Figure 8-4, V_VC rises as the start-up current source charges C_VC and M1 switching is inhibited by the status of the V_C UVLO. The V_B regulator powers the internal converter circuits as V_VC rises. Start-up current is turned off, converter switching is enabled, and a soft-start cycle starts when V_VC exceeds UVLO₁ (approximately 9 V). V_VC falls as it powers both the internal circuits and the switching MOSFET gate. If the converter control-bias output rises to support V_VC before it falls to UVLO₁ – UVLO_1H (approximately 5.5 V), a successful start-up occurs. Figure 8-4 shows a small droop in V_VC while the output voltage rises smoothly and a successful start-up occurs.

Figure 8-4 Power Up and Start

If V_VDD-VSS drops below the lower PoE UVLO (UVLO_R – UVLO_H, approximately 30.5 V), the hotswap MOSFET is turned off, but the converter still runs. The converter stops if V_VC falls below the converter UVLO (UVLO₁ – UVLO_H, approximately 5.5 V), the hotswap is in inrush current limit, or 0% duty cycle is demanded by V_CTL (V_CTL < V_ZDC, approximately 1.5 V), or the converter is in thermal shutdown.