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ZHCSCE7I March 2014 – July 2019 TPS23861

PRODUCTION DATA.

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PW|28
- MPDS364

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6.6 Timing Requirements

–40 ≤ T_J ≤ +125°C, V_VDD = 3.3 V, V_VPWR = 48 V, V_DGND = V_AGND, DGND, KSENSA and KSENSB connected to AGND, and all outputs are unloaded, PoEPn = 0, Positive currents are into pins, R_S = 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB (SEN3 or SEN4), R_SENS = 22 Ω, R_DRAIN = 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating registers loaded with default values (unless otherwise noted)

		MIN	TYP	MAX	UNIT
f_SCL	SCL clock frequency	10		400	kHz
t_LOW	LOW period of SCL clock	1.3			µs
t_HIGH	HIGH period of SCL clock	0.6			µs
t_fo	SDAO output fall time, SDAO, 2.3 → 0.8 V, C_b = 10 pF, 10-kΩ pullup to 3.3 V	21		250	ns
t_fo	SDAO output fall time, SDAO, 2.3 → 0.8 V, C_b = 400 pF, 1.3-kΩ pullup to 3.3 V	60		250	ns
C_I2C	SCL capacitance			10	pF
C_{I2C_SDA}	SDAI, SDAO capacitance			6	pF
t_SU,DATW	Data set-up time (write operation)	100			ns
t_SU,DATR	Data set-up time (read operation), SDAO, 2.3 ↔ 0.8 V, C_b = 400 pF, 1.3-kΩ pull up to 3.3 V	600			ns
t_HD,DATW	Data hold time (write operation)	0			ns
t_HD,DATR	Data hold time (read operation)	150		600	ns
t_fSDA	Input fall times of SDAI, 2.3 → 0.8 V	20		250	ns
t_rSDA	Input rise times of SDAI, 0.8 → 2.3 V	20		300	ns
t_r	Input rise time of SCL, 0.8 → 2.3 V	20		300	ns
t_f	Input fall time of SCL, 2.3 → 0.8 V	20		200	ns
t_BUF	Bus free time between a stop and start condition	1.3			µs
t_HD,STA	Hold time after (repeated) start condition	0.6			µs
t_SU,STA	Repeated start condition set-up time	0.6			µs
t_SU,STO	Stop condition set-up time	0.6			µs
t_{FLT_INT}⁽¹⁾	Fault to INT assertion, Time to internally register an interrupt in response to a fault		150		µs
t_{ARA_INT}	ARA to INT negation			500	ns
t_DG	Suppressed spike pulse width, SDAI and SCL	50			ns
t_RDG	RESET input minimum pulse width (deglitch time)			5	µs
t_{WDT_I2C}	I²C Watchdog trip delay	1.1	2.2	3.3	s
t_{STP_AOUT}	Delay STOP bit to A_OUT high during I²C address programming			1.25	µs

(1) These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product warranty.

Figure 1. I²C Timings