ZHCSCE7I March   2014  – July 2019 TPS23861

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Detailed Pin Description
      2. 7.1.2 I2C Detailed Pin Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Detection Resistance Measurement
      2. 7.3.2  Physical Layer Classification
      3. 7.3.3  Class and Detect Fields
      4. 7.3.4  Register State Following a Fault
      5. 7.3.5  Disconnect
      6. 7.3.6  Disconnect Threshold
      7. 7.3.7  Fast Shutdown Mode
      8. 7.3.8  Legacy Device Detection
      9. 7.3.9  VPWR Undervoltage and UVLO Events
      10. 7.3.10 Timer-Deferrable Interrupt Support
      11. 7.3.11 A/D Converter and I2C Interface
      12. 7.3.12 Independent Operation when the AUTO Bit is Set
      13. 7.3.13 I2C Slave Address and AUTO Bit Programming
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off
      2. 7.4.2 Manual
      3. 7.4.3 Semi-Auto
      4. 7.4.4 Auto
      5. 7.4.5 Push-Button Power On Response
      6. 7.4.6 TSTART Indicators of Detect and Class Failures
      7. 7.4.7 Device Power On Initialization
    5. 7.5 Register Map – I2C-Addressable
      1. 7.5.1  Interrupt Register
      2. 7.5.2  Interrupt Enable Register
      3. 7.5.3  Power Event Register
      4. 7.5.4  Detection Event Register
      5. 7.5.5  Fault Event Register
      6. 7.5.6  Start/ILIM Event Register
      7. 7.5.7  Supply Event Register
      8. 7.5.8  Port n Status Register
        1. 7.5.8.1 Port 1 Status Register
        2. 7.5.8.2 Port 2 Status Register
        3. 7.5.8.3 Port 3 Status Register
        4. 7.5.8.4 Port 4 Status Register
      9. 7.5.9  Power Status Register
      10. 7.5.10 I2C Slave Address Register
      11. 7.5.11 Operating Mode Register
      12. 7.5.12 Disconnect Enable Register
      13. 7.5.13 Detect/Class Enable Register
      14. 7.5.14 Port Power Priority Register
      15. 7.5.15 Timing Configuration Register
      16. 7.5.16 General Mask 1 Register
      17. 7.5.17 Detect/Class Restart Register
      18. 7.5.18 Power Enable Register
      19. 7.5.19 Reset Register
      20. 7.5.20 Legacy Detect Mode Register
      21. 7.5.21 Two-Event Classification Register
      22. 7.5.22 Interrupt Timer Register
      23. 7.5.23 Disconnect Threshold Register
        1. 7.5.23.1 Bits Description
      24. 7.5.24 ICUTnm CONFIG Register
        1. 7.5.24.1 ICUT21 CONFIG Register
        2. 7.5.24.2 ICUT43 CONFIG Register
        3. 7.5.24.3 Bits Description
      25. 7.5.25 Temperature Register
      26. 7.5.26 Input Voltage Register
      27. 7.5.27 Port n Current Register
        1. 7.5.27.1 Port 1 Current Register
        2. 7.5.27.2 Port 2 Current Register
        3. 7.5.27.3 Port 3 Current Register
        4. 7.5.27.4 Port 4 Current Register
      28. 7.5.28 Port n Voltage Register
        1. 7.5.28.1 Port 1 Voltage Register
        2. 7.5.28.2 Port 2 Voltage Register
        3. 7.5.28.3 Port 3 Voltage Register
        4. 7.5.28.4 Port 4 Voltage Register
      29. 7.5.29 PoE Plus Register
      30. 7.5.30 Firmware Revision Register
      31. 7.5.31 I2C Watchdog Register
      32. 7.5.32 Device ID Register
      33. 7.5.33 Cool Down/Gate Drive Register
      34. 7.5.34 Port n Detect Resistance Register
        1. 7.5.34.1 Port 1 Detect Resistance Register
          1. 7.5.34.1.1 Port 2 Detect Resistance Register
          2. 7.5.34.1.2 Port 3 Detect Resistance Register
          3. 7.5.34.1.3 Port 4 Detect Resistance Register
      35. 7.5.35 Port n Detect Voltage Difference Register
        1. 7.5.35.1 Port 1 Detect Voltage Difference Register
        2. 7.5.35.2 Port 2 Detect Voltage Difference Register
        3. 7.5.35.3 Port 3 Detect Voltage Difference Register
        4. 7.5.35.4 Port 4 Detect Voltage Difference Register
      36. 7.5.36 Reserved Registers
  8. 8 Application and Implementation
    1. 8.1 Introduction to PoE
    2. 8.2 Application Information
      1. 8.2.1 Kelvin Current Sensing Resistor
      2. 8.2.2 Connections on Unused Ports
    3. 8.3 Typical Application
      1. 8.3.1 Two Port, Auto Mode Application with External Port Reset
        1. 8.3.1.1 Design Requirements
      2. 8.3.2 Four Port, Auto Mode Application
        1. 8.3.2.1 Design Requirements
      3. 8.3.3 Eight Port, Semi-Auto Mode Application Using MSP430 Micro-Controller
        1. 8.3.3.1 Design Requirements
      4. 8.3.4 Detailed Design Procedure
        1. 8.3.4.1 Power Pin Bypass Capacitors
        2. 8.3.4.2 Per Port Components
        3. 8.3.4.3 System Level Components (not shown in the schematic diagrams)
      5. 8.3.5 Application Curves
    4. 8.4 System Examples
      1. 8.4.1 Overcurrent and Overload Protection
      2. 8.4.2 Inrush Protection
      3. 8.4.3 ICUT Current Limit
      4. 8.4.4 Foldback Protection (ILIM)
      5. 8.4.5 Kelvin Current Sensing Resistor
  9. 9 Power Supply Recommendations
    1. 9.1 VDD
    2. 9.2 VPWR
    3. 9.3 VPWR-RESET Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Port Current Kelvin Sensing
    2. 10.2 Layout Example
      1. 10.2.1 Component Placement and Routing Guidelines
        1. 10.2.1.1 Power Pin Bypass Capacitors
        2. 10.2.1.2 Per-Port Components
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.7 Switching Characteristics

–40 ≤ TJ ≤ +125°C, VVDD = 3.3 V, VVPWR = 48 V, VDGND = VAGND, DGND, KSENSA and KSENSB connected to AGND, and all outputs are unloaded, PoEPn = 0, Positive currents are into pins, RS = 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB (SEN3 or SEN4), RSENS = 22 Ω, RDRAIN = 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating registers loaded with default values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
δIfault Duty cycle of IPORT with current fault 5.5% 6.7%
tOVLD ICUT time limit TICUT = 00, default as supplied 50 70 ms
TICUT = 01 25 35 ms
TICUT = 10 100 140 ms
TICUT = 11 200 280 ms
tLIM ILIM time limit POEPn = 0, default as supplied 50 70 ms
POEPn = 1, TLIM = 00 50 70 ms
POEPn = 1, TLIM = 01 28.4 30 34 ms
POEPn = 1, TLIM = 10 14.7 15.5 17 ms
POEPn = 1, TLIM = 11 9.025 11.5 ms
tSTART Maximum current limit duration in port start-up TSTART = 00, default as supplied 50 70 ms
TSTART = 01 25 35 ms
TSTART = 10 100 140 ms
tDET Four-point detection duration Time to complete a detection 275 500 ms
tDET_BOFF Pause between detection attempts VVPWR – VDRAINn > 2.5 V 300 400 500 ms
VVPWR – VDRAINn < 2.5 V 0 150 ms
tCLE Classification duration 1st and 2nd class event, Auto Mode, Semi-Auto Mode, from detection complete 6.5 13 ms
tpdc Classification duration 1-event physical layer class timing, Auto Mode and Semi-Auto Mode, from detection complete 6.5 13 ms
Manual mode, from beginning of classification 6.5 14 ms
tME Mark duration 1st and 2nd mark event, from class 4 complete 6 12 ms
tp(on) Port power-on delay Manual mode, from port turn-on command to port turn on completed 4 ms
ted Fault delay timing. Delay before next attempt to power a port following power removal due to fault condition ICUT , ILIM or start fault, Auto Mode, Semi-Auto Mode,
CLDN = 0X, default as supplied		 0.8 1 1.2 s
ICUT , ILIM or start fault, Auto Mode, Semi-Auto Mode,
CLDN = 10		 1.6 2 2.4 s
ICUT , ILIM or start fault, Auto Mode, Semi-Auto Mode,
CLDN = 11		 3.2 4 4.8 s
tMPDO PD maintain power signature dropout time limit TDIS = 00, default as supplied 300 400 ms
TDIS = 01 75 100 ms
TDIS = 10 150 200 ms
TDIS = 11 600 800 ms
tD_off_SHDWN Gate turn-off time from SHTDWN input From SHTDWN to VGATEn < 1 V, VSENn = 0 V 1 5 µs
tP_off_CMD Gate turn-off time from port off command From port off command to VGATEn < 1 V, VSENn = 0 V 900 µs
tP_off_RST Gate turn-off time with RESET pin From RESET low to, VGATEn < 1 V, VSENn = 0 V 1 5 µs
tD_off_SEN Gate turn-off time from SENn input POEPn = 0,
VDRAINn = 1 V , from VSENn pulsed to 0.425 V		 0.9 µs
POEPn = 1,
VDRAINn = 1 V , from VSENn pulsed to 0.62 V		 0.9 µs
tPOR Device power-on-reset delay 23 ms
tRESET Reset time duration from RESET pin 1 5 µs
TPS23861 overcurrent_lusbw2.gifFigure 2. Overcurrent Fault Timing
TPS23861 detect_lusbw2.gifFigure 3. Detection, 1-Event Classification, and Turn On
TPS23861 detect2_lusbw2.gifFigure 4. Detection, 2-Event Classification, and Turn On
TPS23861 VDD_pwr_on_rst_slusbx9.gif
For more information refer to the application note, TPS23861 Power-On Considerations, SLVA723.
Figure 5. VDD Power-On-Reset
TPS23861 VPWR_pwr_on_rst_slusbx9.gif
For more information refer to the application note, TPS23861 Power-On Considerations, SLVA723.
Figure 6. VPWR Power-On-Reset
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